Patents by Inventor Hideki Kotake

Hideki Kotake has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8736064
    Abstract: An interconnect element is provided. A monolithic dielectric element has a first exposed major surface, a plurality of first recesses extending inwardly from the first major surface, and a second exposed major surface remote from the first major surface, a plurality of second recesses extending inwardly from the second major surface. A plurality of first metal interconnect patterns are embedded in the plurality of first recesses and extend in one or more directions along the first major surface. A plurality of second metal interconnect patterns are embedded in the plurality of second recesses and extend in one or more directions along the second major surface. A plurality of non-hollow metal posts extend through the dielectric element between at least some of the plurality of first metal interconnect patterns and at least some of the plurality of second metal interconnect patterns.
    Type: Grant
    Filed: November 8, 2010
    Date of Patent: May 27, 2014
    Assignee: Invensas Corporation
    Inventors: Hideki Kotake, Kiyoshi Hyodo, Inetaro Kurosawa, Yukio Hashimoto, Toku Yoshino, Tomoo Iijima
  • Publication number: 20110057324
    Abstract: An interconnect element is provided. A monolithic dielectric element has a first exposed major surface, a plurality of first recesses extending inwardly from the first major surface, and a second exposed major surface remote from the first major surface, a plurality of second recesses extending inwardly from the second major surface. A plurality of first metal interconnect patterns are embedded in the plurality of first recesses and extend in one or more directions along the first major surface. A plurality of second metal interconnect patterns are embedded in the plurality of second recesses and extend in one or more directions along the second major surface. A plurality of non-hollow metal posts extend through the dielectric element between at least some of the plurality of first metal interconnect patterns and at least some of the plurality of second metal interconnect patterns.
    Type: Application
    Filed: November 8, 2010
    Publication date: March 10, 2011
    Applicant: Tessera Interconnect Materials, Inc.
    Inventors: Hideki Kotake, Kiyoshi Hyodo, Inetaro Kurosawa, Yukio Hashimoto, Toku Yoshino, Tomoo Iijima
  • Publication number: 20080169568
    Abstract: A multilayer interconnect element is provided which includes at least one dielectric element in which metal interconnect patterns are exposed at an outer surface thereof, the metal interconnect patterns having outer surfaces which are co-planar with an exposed outer surface of the dielectric element. In addition, multilayer interconnect elements are provided in which second interconnect elements which do not have co-planar interconnect patterns are integrated therewith as intermediate elements, and the resulting multilayer interconnect element has co-planar interconnect patterns.
    Type: Application
    Filed: August 29, 2007
    Publication date: July 17, 2008
    Applicant: Tessera Interconnect Materials, Inc.
    Inventors: Hideki Kotake, Kiyoshi Hyodo, Inetaro Kurosawa, Yukio Hashimoto, Toku Yoshino, Tomoo Iijima
  • Publication number: 20080136041
    Abstract: An interconnect element is provided which includes a dielectric element having a major surface. Metal interconnect patterns are embedded in recesses which extend inwardly from the major surface, the outer surfaces of the interconnect patterns being substantially co-planar with the major surface and extending in one or more directions of the major surface. A projecting conductive film extends over the major surface in at least one direction parallel to a plane defined by the major surface such that it contacts the dielectric element along at least a portion of the major surface and conductively contacts an outer surface of at least one of the metal interconnect patterns.
    Type: Application
    Filed: May 23, 2007
    Publication date: June 12, 2008
    Applicant: Tessera Interconnect Materials, Inc.
    Inventors: Hideki Kotake, Kiyoshi Hyodo, Inetaro Kurosawa, Yukio Hashimoto, Toku Yoshino, Tomoo Iijima
  • Publication number: 20080128288
    Abstract: Methods are provided for manufacturing a wiring circuit element or wiring board in which a set of rough wiring patterns are formed by selectively etching a metal layer of a patternable member which includes a carrier layer having a rough surface and a thin rough-surfaced etch stop layer between the carrier layer and the metal layer. The etch stop layer and wiring patterns are joined to an insulating layer such that the wiring patterns adhere to the insulating layer and the insulating layer acquires a rough surface. Thereafter, the carrier layer and the etch stop layer are removed, after which openings are formed in the insulating layer in contact with at least some of the wiring patterns. A layer of metal is electrolessly plated onto the rough major surface of the insulating layer, and then a conductive wiring pattern is selectively electroplated over the electrolessly plated layer to form plated openings that interconnect at least some of the wiring patterns.
    Type: Application
    Filed: June 8, 2007
    Publication date: June 5, 2008
    Applicant: Tessera Interconnect Materials, Inc.
    Inventors: Yukio Hashimoto, Inetaro Kurosawa, Hideki Kotake