Method of manufacturing a multi-layer wiring board using a metal member having a rough surface
Methods are provided for manufacturing a wiring circuit element or wiring board in which a set of rough wiring patterns are formed by selectively etching a metal layer of a patternable member which includes a carrier layer having a rough surface and a thin rough-surfaced etch stop layer between the carrier layer and the metal layer. The etch stop layer and wiring patterns are joined to an insulating layer such that the wiring patterns adhere to the insulating layer and the insulating layer acquires a rough surface. Thereafter, the carrier layer and the etch stop layer are removed, after which openings are formed in the insulating layer in contact with at least some of the wiring patterns. A layer of metal is electrolessly plated onto the rough major surface of the insulating layer, and then a conductive wiring pattern is selectively electroplated over the electrolessly plated layer to form plated openings that interconnect at least some of the wiring patterns.
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This application is a continuation of U.S. patent application Ser. No. 11/585,064, filed Oct. 23, 2006, which is a continuation of U.S. patent application Ser. No. 11/356,672, filed Feb. 17, 2006, which is based upon and claims the benefit of priority from Japanese Patent Application No. 2005-43784, filed Feb. 21, 2005, the disclosures of which are hereby incorporated by reference herein.
BACKGROUND OF THE INVENTIONWiring boards typically have a wiring layer formed on the surface of an insulating substrate such that the thickness of the wiring layer protrudes above the surface of the insulating substrate. In boards which have high wiring pattern densities, such structures are prone to short-circuiting problems, particularly where contacts to the wiring layers are formed.
Wiring boards are known in which the surfaces of wiring patterns themselves are embedded in the insulating material at the surface of the substrate so as to be coplanar (located at the same plane) with the surface of the insulating material. Examples of such wiring board structures are described in Japanese Examined Patent Application Publication H 6-21619.
(A) As shown in
(B) Next, as shown in
(C) Two wiring members e as shown in
(D) The copper carrier layer a and the nickel layer b are no longer needed and are then removed, as shown in
(E) Next, as shown in
(F) Next, as shown in
Having done so, using this photoresist layer i as a mask for electroplating, copper layer j is deposited electrolytically onto exposed surfaces of the electrolessly formed film to form plated through holes 24.
(G) Next, this photoresist layer is removed and the thin layer h formed by electroless plating is removed to complete the wiring board (
However, the background technology shown in
First, it is difficult to form the copper layer j by the additive process shown in
Second, a selective electrolytic etching process used to form the resist layer i interferes with the additive process of forming the copper layer j, making copper layer j prone to poor connection, poor bonding, and peeling.
Third, upon completing the steps outlined in
These problems, in large part, are due to the exposed surfaces f1 of the glass fiber epoxy resin member f of the insulating material being smooth and failing to adequately grip the electroless and electrolytic metal layers disposed thereon.
SUMMARY OF THE INVENTIONAccording to various embodiments of the invention described herein, methods are provided herein for manufacturing a wiring circuit element or wiring board. In a method in accordance with one embodiment of the invention, a patternable member is provided which includes a carrier layer having a rough surface, a thin etch stop layer overlying the rough surface and a metal layer overlying the etch stop layer. As a result, corresponding surfaces of the etch stop layer and the metal layer overlying and adjacent to the rough surface of the carrier layer are rough. The metal layer is etched selectively to a material of the etch stop layer to form a plurality of wiring patterns and to expose the rough surface of the etch stop layer between the wiring patterns. An insulating layer is joined to the wiring patterns and to the exposed rough surface of the etch stop layer. Thereafter, the carrier layer and the etch stop layer are removed from the insulating layer to expose the wiring patterns and expose a rough major surface of the insulating layer between the wiring patterns. Openings are then formed in the insulating layer in contact with at least some of the wiring patterns. A layer of metal is electrolessly plated onto the rough major surface of the insulating layer and within the openings in the insulating layer. Thereafter, a conductive wiring pattern is selectively electrolytically plated over the electrolessly plated layer and within the openings to form plated openings which conductively interconnect at least some of the wiring patterns. Portions of the electrolessly plated layer exposed by the conductive wiring pattern can then be removed.
In accordance with a particular embodiment of the invention, at least two patternable members are used such that first and second exposed surfaces of the insulating layer are joined to the wiring patterns and exposed rough surfaces of the etch stop layers. In such embodiment, the step of forming openings in the insulating layer includes forming through holes extending from the first surface through the insulating layer to the second surface. In addition, the step of selectively electrolytically plating a conductive wiring pattern conductively interconnects wiring patterns exposed at the first surface with wiring patterns exposed at the second surface of the insulating layer.
In accordance with one or more embodiments of the invention, the etch stop layer includes a metal which is not attacked by an etchant which attacks a metal included in the metal layer overlying the etch stop layer.
Preferably, the etch stop layer consists essentially of nickel and the carrier layer and the metal layer overlying the etch stop layer each consists essentially of copper.
In a particular embodiment of the invention, the patternable member is formed by forming the thin etch stop layer over the rough surface of the carrier layer and forming a second metal layer over the etch stop layer. Preferably, the carrier layer includes a metal.
The roughness of the exposed surface of the carrier layer in contact with the etch stop layer is such that it has unevenness of between about 0.1 micron and about 10 microns.
Preferably, a solder mask is formed to overlie surfaces of the wiring circuit element in such manner that the solder mask exposes the electrolytically plated conductive wiring patterns.
In accordance with one or more preferred aspects of the invention, the wiring patterns are embedded in the insulating layer such that the rough major surface of the insulating layer is co-planar with exposed major surfaces of the wiring patterns.
In accordance with another embodiment of the invention, a method of manufacturing a multi-layer wiring circuit element is provided. In such method, a first patternable member and a second patternable member are provided in which each of the first and second patternable members includes a carrier layer having a rough surface, a thin etch stop layer overlying the rough surface and a metal layer overlying the etch stop layer. In this way, corresponding surfaces of the etch stop layer and the metal layer overlying and adjacent to the rough surfaces of the carrier layer are rough. The metal layers of the first and second patternable members are etched selective to a material of the etch stop layer to form first wiring patterns overlying the etch stop layer of the first patternable member and form second wiring patterns overlying the etch stop layer of the second patternable member and expose the rough surfaces of the etch stop layers in areas exposed by the first or second wiring patterns. Thereafter, the first and second insulating layers are joined to the wiring patterns and exposed etch stop layers of the first and second patternable members, respectively. An interconnection element including at least a third insulating layer is subsequently joined to the first and second insulating layers, the interconnection element having a plurality of interconnect wiring patterns extending in one or more directions parallel to an exposed surface of the third insulating layer. Thereafter, the carrier layers and the etch stop layers are removed to expose the wiring patterns joined to the first and second insulating layers and rough major surfaces of the first and second insulating layers between the wiring patterns. Through holes are formed which extend through the first, second and third insulating layers, the through holes contacting at least some of the wiring patterns. Subsequently, a layer of metal is electrolessly plated onto the rough major surfaces of the first and second insulating layers and within the through holes. Thereafter, conductive wiring patterns are selectively electrolytically plated over the electrolessly plated layers and within the through holes. Portions of the electrolessly plated layers exposed between the electrolytically plated conductive wiring patterns are removed.
In a preferred embodiment of the invention, blind openings are formed which extend through at least one of the first and second insulating layers to the interconnect wiring patterns. In such case, the step of selectively electrolytically plating conductive wiring patterns includes electrolytically plating the conductive wiring patterns in the blind openings to connect the interconnect wiring patterns with at least some of the first or second wiring patterns.
Preferably, the interconnect wiring patterns of the interconnection element are disposed in a plurality of wiring layers separated by respective insulating layers, and the interconnection element further includes plated through holes which conductively interconnect the plurality of wiring layers of the interconnection element.
In the embodiments of the invention described below, one of the major surfaces of a carrier layer which serves as a member for the manufacture of a circuit board is a rough surface. This rough surface is transferred to a metal etch stop layer and, in turn, to a metal wiring layer formed on that rough surface. The rough surface is then transferred to insulating material which forms a base of the board. The insulating material which forms the base of the wiring board preferably includes epoxy resin in which glass fibers are embedded. After the metal wiring layer is patterned, the metal wiring layer and the insulating material retain the rough surface when the carrier layer is removed.
A preferred method of interconnecting wiring layers of the wiring board is to form through holes and then line the through holes by electroless plating of copper or other metal. A resist layer is then formed and copper or other metal is then selectively deposited by electrolytic plating. Preferably a dry resist layer is used as this resist layer.
The embodiments of the invention provided herein are described with reference to the drawings.
(A) As shown in
(B) Next, as shown in
Like the surface 4 of the carrier layer, the surface of the etch stop layer 6 is also rough. This is because the etch stop layer 6 is thin, preferably under 1.0 microns and follows the roughness of the uneven major surface 4 of the carrier layer 2.
(C) Next, as shown in
(D) Next, as shown in
(E) Next, as shown in
At this time, the rough surfaces of the metal members 10a are transferred to the surfaces 16 of the insulating material 14 to make them rough as well, except where the insulating material contacts the wiring patterns 12, 12 . . . . The rough surfaces of the etch stop layers 6 are transferred to the major surfaces 16 of the insulating material 14.
Although in the embodiment illustrated in
(F) Next, as shown in FIG. (F), the carrier layer 2 and the etch stop layer 6 are removed because they are no longer needed. In so doing, a wiring board is completed in which the exposed surfaces 15 of the wiring patterns 12, 12, . . . are coplanar with the exposed major surfaces 16 of the insulating material 14 and both the exposed surfaces 15 of the wiring patterns and the exposed major surfaces of the insulating material are rough surfaces.
(G) Next, as shown in
(H) Next, as shown in
(I) Next, as shown in
(J) Next, as shown in
(K) Next, as shown in
(L) Next, as shown in
(M) Next, as shown in
This solder resist layer 26 is formed on the rough surface of the insulating material 14. Therefore, the solder resist layer strongly adheres to the underlying insulating material 14, avoiding the above-described problems of poor bonding and the tendency to peel.
(A) First, a member for the manufacture of a wiring board 10 is prepared in a manner as described above with reference to
(B) Next, as shown in
(C) As shown in
(D) Next, referring to
Next, the carrier layers 2,2 of the members 10a, 10a on both sides are removed, and the etch stop layers 6, 6 are removed, leaving rough surfaces 15 of the wiring patterns and rough surfaces 41 of the insulating material 40 exposed.
After that, blind openings 46, 46, serving as the interlayer connection means, and through holes 48 are formed, to provide the structure shown in
Next, referring to
In such manner, plated through holes 54 and plated blind openings 56 provide interlayer connections between the wiring patterns 12 on each side of the insulating material 40.
(F) Next, as shown in
(G) Next, as shown in
(H) Next, as shown in
The embodiment shown in
Thus, this embodiment of the invention facilitates manufacture of a more multi-layered structure, a greater diversity of through-hole shapes, and can facilitate the manufacture of wiring boards with a variety of structures.
Layers including copper or the like used to plate the through holes are formed using electrolytic plating of copper or the like in this particular embodiment, but the invention is not limited to this, and can be formed using, for example, conductive fillers.
Although the invention herein has been described with reference to particular embodiments, it is to be understood that these embodiments are merely illustrative of the principles and applications of the present invention. It is therefore to be understood that numerous modifications may be made to the illustrative embodiments and that other arrangements may be devised without departing from the spirit and scope of the present invention as defined by the appended claims.
Claims
1. A method of manufacturing a wiring circuit element comprising the steps of:
- providing a patternable member including a carrier layer having a rough surface, a thin etch stop layer overlying the rough surface and a metal layer overlying the etch stop layer such that corresponding surfaces of the etch stop layer and the metal layer overlying and adjacent to the rough surface of the carrier layer are rough;
- etching the metal layer selectively to a material of the etch stop layer to form a plurality of wiring patterns and to expose the rough surface of the etch stop layer between the wiring patterns;
- joining an insulating layer to the wiring patterns and to the exposed rough surface of the etch stop layer;
- thereafter removing the carrier layer and the etch stop layer from the insulating layer to expose the wiring patterns and expose a rough major surface of the insulating layer between the wiring patterns;
- forming openings in the insulating layer in contact with at least some of the wiring patterns;
- electrolessly plating a layer of metal onto the rough major surface of the insulating layer and within the openings in the insulating layer;
- selectively electrolytically plating a conductive wiring pattern over the electrolessly plated layer and within the openings to form plated openings which conductively interconnect at least some of the wiring patterns; and
- removing portions of the electrolessly plated layer exposed by the conductive wiring pattern.
2. The method as claimed in claim 1, wherein exposed first and second opposite surfaces of the insulating layer are joined to the wiring patterns and exposed rough surfaces of the etch stop layers of at least two of the patternable members, the step of forming openings in the insulating layer includes forming through holes extending from the first surface through the insulating layer to the second surface, and the step of selectively electrolytically plating a conductive wiring pattern conductively interconnects wiring patterns exposed at the first surface with wiring patterns exposed at the second surface of the insulating layer.
3. The method as claimed in claim 1, wherein the etch stop layer includes a metal which is not attacked by an etchant which attacks a metal included in the metal layer overlying the etch stop layer.
4. The method as claimed in claim 3, wherein the etch stop layer consists essentially of nickel and the carrier layer and the metal layer overlying the etch stop layer consist essentially of copper.
5. The method as claimed in claim 4, wherein the patternable member is formed by forming the thin etch stop layer over the rough surface of the carrier layer and forming a second metal layer over the etch stop layer.
6. The method as claimed in 3, wherein the carrier layer includes a metal.
7. The method as claimed in claim 1, wherein the exposed surface of the carrier layer in contact with the etch stop layer has unevenness of between about 0.1 micron and about 10 microns.
8. The method as claimed in claim 5, further comprising forming a solder mask overlying surfaces of the wiring circuit element, the solder mask exposing the electrolytically plated conductive wiring patterns.
9. The method as claimed in claim 1, wherein the wiring patterns are embedded in the insulating layer such that the rough major surface of the insulating layer is co-planar with major surfaces of the wiring patterns.
10. A method of manufacturing a multi-layer wiring circuit element, comprising the steps of:
- providing a first patternable member and a second patternable member, each of the first and second patternable members including a carrier layer having a rough surface, a thin etch stop layer overlying the rough surface and a metal layer overlying the etch stop layer, such that corresponding surfaces of the etch stop layer and the metal layer overlying and adjacent to the rough surfaces of the carrier layer are rough;
- etching the metal layers of the first and second patternable members selective to a material of the etch stop layer to form first wiring patterns overlying the etch stop layer of the first patternable member and to form second wiring patterns overlying the etch stop layer of the second patternable member and to expose the rough surfaces of the etch stop layers in areas exposed by the first or second wiring patterns;
- joining first and second insulating layers to the wiring patterns and exposed etch stop layers of the first and second patternable members, respectively;
- joining an interconnection element including at least a third insulating layer to the first and second insulating layers, the interconnection element including a plurality of interconnect wiring patterns extending in one or more directions parallel to an exposed surface of the third insulating layer;
- thereafter removing the carrier layers and the etch stop layers to expose the wiring patterns joined to the first and second insulating layers and rough major surfaces of the first and second insulating layers between the wiring patterns;
- forming through holes extending through the first, second and third insulating layers, the through holes contacting at least some of the wiring patterns;
- electrolessly plating a layer of metal onto the rough major surfaces of the first and second insulating layers and within the through holes;
- selectively electrolytically plating conductive wiring patterns over the electrolessly plated layers and within the through holes; and
- removing portions of the electrolessly plated layers exposed between the electrolytically plated conductive wiring patterns.
11. The method as claimed in claim 10, further comprising forming blind openings extending through at least one of the first and second insulating layers to the interconnect wiring patterns, wherein the step of selectively electrolytically plating conductive wiring patterns includes electrolytically plating the conductive wiring patterns in the blind openings to connect the interconnect wiring patterns with at least some of the first or second wiring patterns.
12. The method as claimed in claim 10, wherein the interconnect wiring patterns of the interconnection element are disposed in a plurality of wiring layers separated by respective insulating layers, the interconnection element further including plated through holes conductively interconnecting the plurality of wiring layers of the interconnection element.
13. The method as claimed in claim 12, further comprising forming a solder mask overlying surfaces of the multi-layer wiring element, the solder mask exposing the electrolytically plated conductive wiring patterns.
14. The method as claimed in claim 10, wherein the etch stop layer of each patternable member consists essentially of nickel and the carrier layer and the metal layer overlying the etch stop layer consist essentially of copper.
15. The method as claimed in claim 14, wherein each of the first and second patternable members is formed by forming a thin etch stop layer over the rough surface of the carrier layer and forming a second metal layer over the etch stop layer.
16. The method as claimed in 13, wherein the carrier layer of each patternable member includes a metal.
17. The method as claimed in claim 10, wherein the carrier layer of each patternable member has unevenness of between about 0.1 micron and about 10 microns.
Type: Application
Filed: Jun 8, 2007
Publication Date: Jun 5, 2008
Applicant: Tessera Interconnect Materials, Inc. (San Jose, CA)
Inventors: Yukio Hashimoto (Tokyo), Inetaro Kurosawa (Tokyo), Hideki Kotake (Tokyo)
Application Number: 11/811,066
International Classification: C25D 5/02 (20060101);