Abstract: The present invention provides a microcontroller which can continue operation even at the time of a failure without making a memory redundant to suppress increase in chip area. The microcontroller includes three or more processors executing the same process in parallel and a storage device. The storage device includes a memory mat having a storage region which is not redundant, an address selection part, a data output part, and a failure recovery part. The address selection part selects a storage region in the memory mat on the basis of three or more addresses issued at the time of an access by the processors. The data output part reads data from the storage region in the memory mat selected by the address selection part. The failure recovery part corrects or masks a failure of predetermined number or less which occurs in the memory mat, the address selection part, and the data output part.

Abstract: The present invention provides a microcontroller which can continue operation even at the time of a failure without making a memory redundant to suppress increase in chip area. The microcontroller includes three or more processors executing the same process in parallel and a storage device. The storage device includes a memory mat having a storage region which is not redundant, an address selection part, a data output part, and a failure recovery part. The address selection part selects a storage region in the memory mat on the basis of three or more addresses issued at the time of an access by the processors. The data output part reads data from the storage region in the memory mat selected by the address selection part. The failure recovery part corrects or masks a failure of predetermined number or less which occurs in the memory mat, the address selection part, and the data output part.

Abstract: A microcomputer includes: a plurality of register lists having a plurality of register patterns, respectively, wherein each of plurality of register patterns designates registers, data of which are to be saved in a data memory; an instruction fetch control circuit configured to fetch instruction code from an instruction memory in response to an interrupt request issued based on occurrence of an interrupt factor; and a register data saving control circuit configured to acquire one register pattern from one of the plurality of register lists in response to the interrupt request, and issue a microinstruction based on the acquired register pattern in response to the interrupt request. An instruction executing section is configured to execute the microinstruction prior to the fetched instruction code, to save the data of registers designated based on the acquired register pattern in the data memory.

Abstract: A microcomputer includes: a plurality of register lists having a plurality of register patterns, respectively, wherein each of plurality of register patterns designates registers, data of which are to be saved in a data memory; an instruction fetch control circuit configured to fetch instruction code from an instruction memory in response to an interrupt request issued based on occurrence of an interrupt factor; and a register data saving control circuit configured to acquire one register pattern from one of the plurality of register lists in response to the interrupt request, and issue a microinstruction based on the acquired register pattern in response to the interrupt request. An instruction executing section is configured to execute the microinstruction prior to the fetched instruction code, to save the data of registers designated based on the acquired register pattern in the data memory.

Abstract: A microcomputer includes: a plurality of register lists having a plurality of register patterns, respectively, wherein each of plurality of register patterns designates registers, data of which are to be saved in a data memory; an instruction fetch control circuit configured to fetch instruction code from an instruction memory in response to an interrupt request issued based on occurrence of an interrupt factor; and a register data saving control circuit configured to acquire one register pattern from one of the plurality of register lists in response to the interrupt request, and issue a microinstruction based on the acquired register pattern in response to the interrupt request. An instruction executing section is configured to execute the microinstruction prior to the fetched instruction code, to save the data of registers designated based on the acquired register pattern in the data memory.

Abstract: A processor system according to an exemplary aspect of the present invention includes a first processor, a second processor, a control unit, a signal line group, and a selection circuit. The control unit switches an operation mode between a lock step mode for the first and second processors to execute the same instruction stream and a free step mode for the first and second processors to execute different instruction streams. The signal line group includes at least one signal line disposed between a first memory circuit included in the first processor and a second memory circuit included in the second processor. The signal line group is capable of transferring a storage state of the first memory circuit to the second memory circuit. The selection circuit is capable of switching a connection destination of the second memory circuit between the second processor and the signal line group.

Abstract: Disclosed herein is a processor system including a specific code area setting register holding a first set value corresponding to an address range of a specific code area in which a specific program is stored; a peripheral device having a specific data storage area for storing specific data to be used by the specific program; a processor element outputting an access request to the peripheral device upon executing programs including the specific program, and determining whether the program executed by reference to the first set value is the specific program, and a safety guard controlling access to the specific data storage area depending on whether the access request results from the execution of the specific program.

Abstract: Provided is a microprocessor including a complex-MAC unit that operates in response to a complex-MAC instruction. The complex-MAC unit receives first and second complex data (each having 2m-bit length) from a first register having a register length of at least 2m+1 bits, and also receives third and fourth complex data (each having 2m-bit length) from a second register having a register length of at least 2m+1 bits, to calculate a sum of real parts or imaginary parts of a complex product of the first and third complex data and a complex product of the second and fourth complex data. The complex-MAC unit adds the obtained sum of the real parts or imaginary parts to a stored value of the third register, and overwrites the third register with the cumulative total value. The third register has a register length of at least 2m+2 bits.

Abstract: A filter operation circuit of a microprocessor executes an IIR filter operation by using data provided from registers R0 to R2 and outputs one sample of data Y[n] subjected to filter operation and transfer data P[n] to be used in the next IIR filter operation. Register R0 provides filter coefficients to the filter operation circuit. Register R1 provides past transfer data P[n?1] and P[n?2] to the filter operation circuit and is overwritten and updated with new transfer data P[n] output from the filter operation circuit. Register R2 holds multiple samples of data X[n] to X[n+3] to be subjected to filter operation and provides X[n] to the filter operation circuit. An area of register R2 in which X[n] has been held is overwritten and updated with Y[n].

Abstract: Provided is a parallel comparison/selection operation apparatus which efficiently executes a search for a maximum value or a search for a minimum value with an index. The parallel comparison/selection operation apparatus includes a vector comparison/selection unit 242 that compares each element included in vector data 1 and vector data 2 for each corresponding element using the vector data 1 and the vector data 2, selects one element of the vector data 1 and the vector data 2 based on the comparison result, and generates vector data 3 including the selected element, and an index vector selection unit 243 that selects one element of an index vector 1 and an index vector 2 based on the comparison result vector using the index vector 1 of the vector data 1, the index vector 2 of the vector data 2, and the comparison result vector to generate and output an index vector 3 including the selected element.

Abstract: A microcomputer includes: a plurality of register lists having a plurality of register patterns, respectively, wherein each of plurality of register patterns designates registers, data of which are to be saved in a data memory; an instruction fetch control circuit configured to fetch instruction code from an instruction memory in response to an interrupt request issued based on occurrence of an interrupt factor; and a register data saving control circuit configured to acquire one register pattern from one of the plurality of register lists in response to the interrupt request, and issue a microinstruction based on the acquired register pattern in response to the interrupt request. An instruction executing section is configured to execute the microinstruction prior to the fetched instruction code, to save the data of registers designated based on the acquired register pattern in the data memory.

Abstract: A data storing part outputs n-bit data according to a reading address generated by an address generator. A peak value candidate selecting part selects a maximum value of a plurality of elements forming the n-bit data as a peak value candidate when data of one data unit is expressed as one element and outputs the peak value candidate together with a positional information indicating an element position of the peak value candidate. When the peak value candidate is larger than a peak value held in a peak value holding part, a peak value calculating part calculates an address of the peak value candidate using the positional information of the peak value candidate and a reading address, outputs the address and the peak value candidate to the peak value holding part, and updates content held in the peak value holding part.

Abstract: A bus system includes one or more bus masters, one or more bus slaves, and a response unit. When an access request to a resource of a bus slave is sent from a bus master, the response unit outputs a wait response that is either a blocking wait response to cause the bus master to perform a blocking wait operation or a non-blocking wait response to cause it to perform a non-blocking wait operation to the bus master if the bus slave is in the wait state.

Abstract: One exemplary embodiment includes a processor including a plurality of execution units and an instruction unit. The instruction unit discriminates whether an instruction is a target instruction for which determination about availability of parallel issue based on dependency among instructions is to be made with respect to each instruction contained in an instruction stream. When a first instruction contained in the instruction stream is the target instruction, the instruction unit adjusts the number of instructions to be issued in parallel to the plurality of execution units based on a detection result of dependency among the first instruction and at least one subsequent instruction. Further, when the first instruction is not the target instruction, the instruction unit issues a group of a predetermined fixed number of instructions including the first instruction in parallel to the plurality of execution units unconditionally regardless of a detection result of dependency among the instruction group.

Abstract: A performance evaluation device includes an event counter unit that counts events occurring by execution of an evaluation target program from arrival of a measurement start signal indicating a measurement start point of a measurement section preset to the evaluation target program to arrival of a measurement stop signal indicating a measurement stop point of the measurement section, and an iteration counter unit that counts iterations of the measurement section to be iterated based on at least one of the measurement start signal and the measurement stop signal.

Abstract: A processor system according to an exemplary aspect of the present invention includes a first processor, a second processor, a control unit, a signal line group, and a selection circuit. The control unit switches an operation mode between a lock step mode for the first and second processors to execute the same instruction stream and a free step mode for the first and second processors to execute different instruction streams. The signal line group includes at least one signal line disposed between a first memory circuit included in the first processor and a second memory circuit included in the second processor. The signal line group is capable of transferring a storage state of the first memory circuit to the second memory circuit. The selection circuit is capable of switching a connection destination of the second memory circuit between the second processor and the signal line group.

Abstract: Provided is a microprocessor including a complex-MAC unit that operates in response to a complex-MAC instruction. The complex-MAC unit receives first and second complex data (each having 2m-bit length) from a first register having a register length of at least 2m+1 bits, and also receives third and fourth complex data (each having 2m-bit length) from a second register having a register length of at least 2m+1 bits, to calculate a sum of real parts or imaginary parts of a complex product of the first and third complex data and a complex product of the second and fourth complex data. The complex-MAC unit adds the obtained sum of the real parts or imaginary parts to a stored value of the third register, and overwrites the third register with the cumulative total value. The third register has a register length of at least 2m+2 bits.

Abstract: A branch prediction device predicts a branching probability in which a branch condition of a conditional branch instruction read out from an instruction memory storing an instruction is satisfied. A branch prediction entry part included in the branch prediction device stores prediction information as to whether or not the branch condition of the conditional branch instruction is satisfied. An entry update part included in the branch prediction device predicts the branching probability when the conditional branch instruction is executed next time based on a branch direction and updates the prediction information when the branch condition is satisfied by executing the conditional branch instruction.

Abstract: A data storing part outputs n-bit data according to a reading address generated by an address generator. A peak value candidate selecting part selects a maximum value of a plurality of elements forming the n-bit data as a peak value candidate when data of one data unit is expressed as one element and outputs the peak value candidate together with a positional information indicating an element position of the peak value candidate. When the peak value candidate is larger than a peak value held in a peak value holding part, a peak value calculating part calculates an address of the peak value candidate using the positional information of the peak value candidate and a reading address, outputs the address and the peak value candidate to the peak value holding part, and updates content held in the peak value holding part.

Abstract: A microprocessor has an instruction decode portion, a register file, a complex operation unit, and a data storage position determining mechanism. The complex operation unit performs complex operation, including complex multiplication, using first and second complex number data supplied from the register file based on an instruction decoded by the instruction decode portion, and outputs the result of the complex operation toward the register file. Furthermore, the data storage position determining mechanism determines the storage positions of the real part and imaginary part of output data of the complex operation unit in the register file such that the storage order of the real part and imaginary part of the output data in the register file is consistent with the storage orders of the real parts and imaginary parts of the first and second complex number data.