Abstract: A processor includes an instruction decoder, an instruction execution part and a register file. The instruction decoder is adapted to decode an instruction. The instruction execution part is adapted to execute processing corresponding to the instruction decoded by the instruction decoder. The register file is capable of storing load data from a data memory and supplying input data to the instruction execution part. The register file includes a plurality of registers, each of which is capable of holding a plurality of bits of data. Furthermore, the register file is configured to update the data held by the plurality of registers by shifting the data held by the plurality of registers among the plurality of registers.

Abstract: A filter operation circuit of a microprocessor executes an IIR filter operation by using data provided from registers R0 to R2 and outputs one sample of data Y[n] subjected to filter operation and transfer data P[n] to be used in the next IIR filter operation. Register R0 provides filter coefficients to the filter operation circuit. Register R1 provides past transfer data P[n?1] and P[n?2] to the filter operation circuit and is overwritten and updated with new transfer data P[n] output from the filter operation circuit. Register R2 holds multiple samples of data X[n] to X[n+3] to be subjected to filter operation and provides X[n] to the filter operation circuit. An area of register R2 in which X[n] has been held is overwritten and updated with Y[n].

Abstract: Memory protection apparatus to protect memory area to realize high interruption response and prohibit from access to the memory area that is previously designated. The memory area data registers 132 (1) to (m), respectively, retain data which designate the accessible memory area in the processing corresponding to interruption of the group number corresponding to it. Selection circuit 133 selects any of the memory area data registers 132 (1) to (m) according to the group number retained by the group number register 131, and outputs data that designates selected memory area retained by the memory area data registers 132. Address bus watching part 106 watches generation of illegal memory access of the processor according to the data designating the memory area output by the selection circuit 133.

Abstract: A bus system includes one or more bus masters, one or more bus slaves, and a response unit. When an access request to a resource of a bus slave is sent from a bus master, the response unit outputs a wait response that is either a blocking wait response to cause the bus master to perform a blocking wait operation or a non-blocking wait response to cause it to perform a non-blocking wait operation to the bus master if the bus slave is in the wait state.

Abstract: Interrupt controlling circuit by which only a desired one(s) of plural interrupts may readily be masked. An interrupt factor controlling module 105 is provided for each interrupt. An interrupt group setting register 154 holds a group number of an interrupt signal INT entered to the interrupt factor controlling module 105. An interrupt group mask register 103 holds, for each group, information as to whether or not an interrupt belonging to a group in question is to be masked. In case an interrupt has occurred and the group of the group number of the interrupt, as held by the interrupt group setting register 154, is specified by the interrupt group mask register 103 as being to be masked, the interrupt mask circuit 152 masks the interrupt.

Abstract: Interrupt controlling circuit by which only a desired one(s) of plural interrupts may readily be masked. An interrupt factor controlling module 105 is provided for each interrupt. An interrupt group setting register 154 holds a group number of an interrupt signal INT entered to the interrupt factor controlling module 105. An interrupt group mask register 103 holds, for each group, information as to whether or not an interrupt belonging to a group in question is to be masked. In case an interrupt has occurred and the group of the group number of the interrupt, as held by the interrupt group setting register 154, is specified by the interrupt group mask register 103 as being to be masked, the interrupt mask circuit 152 masks the interrupt.

Abstract: Memory protection apparatus to protect memory area to realize high interruption response and prohibit from access to the memory area that is previously designated. The memory area data registers 132 (1) to (m), respectively, retain data which designate the accessible memory area in the processing corresponding to interruption of the group number corresponding to it. Selection circuit 133 selects any of the memory area data registers 132 (1) to (m) according to-the group number retained by the group number register 131, and outputs data that designates selected memory area retained by the memory area data registers 132. Address bus watching part 106 watches generation of illegal memory access of the processor according to the data designating the memory area output by the selection circuit 133.

Abstract: In order to immediately respond to an access request from a processor with reduced power consumption, a requested information is read out from a cache memory 31 or information buffers 421 to 421 and supplied to the processor when comparators 343 to 3410 output hit signals.

Abstract: In order to immediately respond to an access request from a processor with reduced power consumption, a requested information is read out from a cache memory 31 or information buffers 421 to 424 and supplied to the processor when comparators 343 to 3410 output hit signals.

Abstract: In an information processing apparatus, an interrupt control apparatus and method controls interrupt request inputs with respect to a processor. The interrupt control apparatus includes an interrupt flag holding circuit for holding a plurality of flags indicative of interrupt factors with respect to the respective interrupt request inputs and also holds a plurality of interrupt levels representative of priority orders of the interrupt request inputs. An interrupt level judging circuit judges an interrupt level having a top priority and also outputs an interrupt request to the processor. An interrupt vector generating circuit generates an interrupt vector in response to the held interrupt factor and an interrupt vector outputting circuit outputs the held interrupt vector to the processor.