Abstract: A stator core of a motor has a plurality of oil return passages extending through one surface and the other surface of the core. On the other surface of the stator core, a hydraulic diameter of each oil return passage is 5 mm or larger, and a ratio of a total area of the oil return passages to an area of a virtual circle having a diameter equal to a maximum outer diameter of the stator core is 5 to 15%. Lubricating oil accumulated on the other surface side of the stator core is returned to an oil reservoir through the oil return passages, and shortage of oil in the oil reservoir is prevented. Furthermore, a cross sectional area of the stator core can be securely kept, and motor efficiency is maintained.

Abstract: An electrostatic protection circuit includes a first impurity region, a second impurity region, a first electrode, a third impurity region, a fourth impurity region, a second electrode, a fifth impurity region, a sixth impurity region, a third electrode, a gate insulating film, and a fourth electrode.

Abstract: An air processing apparatus is provided with an air processing apparatus main body, to which a plurality of office apparatuses are connectable. A suction air interface for connecting the office apparatuses and the air processing apparatus main body together is provided so that air in the office apparatuses can be received into the air processing apparatus main body. An air processing portion is also provided in the air processing apparatus main body, to process the air received into the air processing apparatus main body through the suction air interface.

Abstract: Compositions, foods, and beverages which contain a salt-free or a reduced-salt fermented soybean paste-like food material in which the salt content is 5% or less, obtained by hydrolyzing soybean by a koji mold have an excellent anti-obesity action.

Abstract: In an LED lamp, a copper film is first formed on a substrate by plating. A resist is then bonded onto the copper film so that shaped like a ring viewed from the whole of the LED lamp. A nickel and a gold film are formed on a portion of the copper film where the resist is not bonded. Next, an adhesive agent is applied onto a bottom of the lamp house so that the lamp house is bonded onto the substrate through the adhesive agent. A transparent epoxy resin is packed in the frame of the lamp house and hardened by heating to perform resin sealing. Since the resist is bonded onto the surface of copper having a large number of fine irregularities sufficient to ensure a large contact area and excellent in adhesion, separation can be prevented from being caused by thermal stress.

Abstract: A counter reflecting surface is provided opposite to a light emitting element in its light emitting surface. A side reflecting member having an inclined reflecting surface is provided apart from and so as to surround the light emitting element. A phosphor layer is provided on the counter reflecting surface and the reflecting surface of the side reflecting member.

Abstract: An image processing apparatus includes a converter converting an interlace image including a first number of pixels into a first progressive image, an interpolator interpolating the first progressive image to generate a second progressive image including a second number of pixels, a classification unit classifying, in accordance with a feature of the second progressive image, into classes, subject pixels forming a third progressive image, which serves as a target image, including the second number of pixels and having a quality higher than the second progressive image, a storage unit storing a prediction coefficient for each of the classes obtained by conducting learning using a plurality of progressive images, each including the second number of pixels, and a computation unit performing computation using the second progressive image and the prediction coefficient for each of the classes to determine the third progressive image from the second progressive image.

Abstract: An image processing apparatus includes an interlace-progressive converter converting an interlace input image into a progressive intermediate image, a motion-vector detector detecting motion vectors of the input image by using a distance shorter than the pixel interval of the intermediate image, a cyclic-coefficient setting unit setting, on the basis of a vertical motion, a first cyclic coefficient for a first type of pixel and a second cyclic coefficient for a second type of pixel, a motion compensator motion-compensating, on the basis of the motion vectors, a past progressive output image to generate a motion-compensated image, and an output image generator generating a progressive output image by adding pixel values of the first type of pixels and the second type of pixels of the progressive intermediate image and the motion-compensated image by using the first cyclic coefficient and the second cyclic coefficient as weights.

Abstract: Drying capsinoid-containing chili peppers for capsinoid extraction, such that hot drying is conducted so that, at a minimum, the weight of the capsinoid-containing chili peppers is reduced to not more than 20 percent, and the moisture content to not more than 10 percent, of that of the raw fruit, is useful for obtaining a stable product.

Abstract: Embodiments of the invention provide a support structure for a voice coil that is not easily damaged even when a carriage assembly used in a magnetic disk drive is made thinner. In one embodiment, the voice coil includes a stack of a plurality of layers of aligned windings held between an outer holding portion and an inner holding portion of the carriage assembly. The carriage assembly is formed integrally with the voice coil through injection molding. An outermost peripheral layer is a conductive wire wound a number of turns that falls short of the number of turns required to constitute a complete layer. A step is thereby formed between the outermost peripheral layer and a layer adjacent thereto and inner therefrom. The outer holding portion includes a reinforcement portion formed thereon to cover part of a transverse end face of the voice coil.

Abstract: An air processing apparatus is provided with an air processing apparatus main body to which a plurality of office apparatuses are connectable, a suction air interface for connecting the office apparatuses and the air processing apparatus main body together so that air in the office apparatuses can be received into the air processing apparatus main body, and an air processing portion provided in the air processing apparatus main body for effecting processing on the air received into the air processing apparatus main body through the suction air interface.

Abstract: By stably separating a melting location of a fuse (3) from conductive layers (5A, 5B), reliable melting of the fuse (3) is enabled. A fuse (3) including a fuse body (3A) and two pads (3Ba, 3Bb) connected by this and two conductive layers (5A, 5B) individually connected to the two pads (3Ba, 3Bb) are formed in a multilayer structure on a semiconductor substrate (1). A length of the fuse body (3A) is defined so that the melting location of the fuse (3) becomes positioned in the fuse body (3A) away from the region overlapped on the conductive layer (5A or 5B) when an electrical stress is applied between two conductive layers (5A, 5B) and the fuse (3) is melted.

Abstract: The present invention relates to a semiconductor device including a high withstand voltage MOS transistor and a manufacturing method thereof. The semiconductor device according to the present invention includes a MOS transistor in which a second-conductivity type source region is formed on a first-conductivity type semiconductor region, an offset drain region is interconnected to a second-conductivity type drain region and has a concentration lower than an impurity concentration of a drain region, the offset drain region is composed of a portion that does not overlap a first-conductivity type semiconductor region and a portion that overlaps part of the surface of the first-conductivity type semiconductor region and a gate electrode is formed on the surface extending from a channel region between the source region and the offset drain region to part of the offset drain region through a gate insulating film.

Abstract: A charge injection method for improving the efficiency of generating hot carriers, wherein, for example, electrons are injected at writing and holes are injected at erasing to a charge storage layer of a memory transistor. A positive voltage is applied to the drain region by using a voltage of the source region as a reference, and a voltage having a polarity in accordance with charges to be injected is applied to a gate electrode. A voltage having a voltage value between a source voltage and a drain voltage for turning on a diode made by an N-type source region and a P-type body region is applied to the body region. Then a parasitic bipolar transistor turns on, and, consequently, impact ionization arises on the drain side and an injection charge amount increases.

Abstract: Compositions, foods, and beverages which contain a salt-free or a reduced-salt fermented soybean paste-like food material in which the salt content is 5% or less, obtained by hydrolyzing soybean by a koji mold have an excellent anti-obesity action.

Abstract: A semiconductor device (100) according to the present invention comprises a vertical PNP bipolar transistor (20), an NMOS transistor (50) and a PMOS transistor (60) that are of high dielectric strength, and a P-type semiconductor substrate 1, as shown in FIG. 2. A substrate isolation layer (21) of the PNP bipolar transistor (20), a drain buried layer (51) of the NMOS transistor (50), and a back gate buried layer (61) of the PMOS transistor (60) are formed simultaneously by selectively implanting N-type impurities, such as phosphorous, in the semiconductor substrate (1). This invention greatly contributes to curtailing the processes of fabricating BiCMOS ICs and the like including vertical bipolar transistors with easily controllable performance characteristics, such as a current amplification factor, and MOS transistors with high dielectric strength and makes even more miniaturization of such ICs achievable.

Abstract: A semiconductor device (100) according to the present invention comprises a vertical PNP bipolar transistor (20), an NMOS transistor (50) and a PMOS transistor (60) that are of high dielectric strength, and a P-type semiconductor substrate 1, as shown in FIG. 2. A substrate isolation layer (21) of the PNP bipolar transistor (20), a drain buried layer (51) of the NMOS transistor (50), and a back gate buried layer (61) of the PMOS transistor (60) are formed simultaneously by selectively implanting N-type impurities, such as phosphorous, in the semiconductor substrate (1). This invention greatly contributes to curtailing the processes of fabricating BiCMOS ICs and the like including vertical bipolar transistors with easily controllable performance characteristics, such as a current amplification factor, and MOS transistors with high dielectric strength and makes even more miniaturization of such ICs achievable.

Abstract: A semiconductor device (100) according to the present invention comprises a vertical PNP bipolar transistor (20), an NMOS transistor (50) and a PMOS transistor (60) that are of high dielectric strength, and a P-type semiconductor substrate 1, as shown in FIG. 2. A substrate isolation layer (21) of the PNP bipolar transistor (20), a drain buried layer (51) of the NMOS transistor (50), and a back gate buried layer (61) of the PMOS transistor (60) are formed simultaneously by selectively implanting N-type impurities, such as phosphorous, in the semiconductor substrate (1). This invention greatly contributes to curtailing the processes of fabricating BiCMOS ICs and the like including vertical bipolar transistors with easily controllable performance characteristics, such as a current amplification factor, and MOS transistors with high dielectric strength and makes even more miniaturization of such ICs achievable.

Abstract: A semiconductor device (100) according to the present invention comprises a vertical PNP bipolar transistor (20), an NMOS transistor (50) and a PMOS transistor (60) that are of high dielectric strength, and a P-type semiconductor substrate 1, as shown in FIG. 2. A substrate isolation layer (21) of the PNP bipolar transistor (20), a drain buried layer (51) of the NMOS transistor (50), and a back gate buried layer (61) of the PMOS transistor (60) are formed simultaneously by selectively implanting N-type impurities, such as phosphorous, in the semiconductor substrate (1). This invention greatly contributes to curtailing the processes of fabricating BiCMOS ICs and the like including vertical bipolar transistors with easily controllable performance characteristics, such as a current amplification factor, and MOS transistors with high dielectric strength and makes even more miniaturization of such ICs achievable.

Abstract: A charge injection method for improve efficiency of generating hot carrier, wherein, for example, electrons are injected at writing and holes are injected at erasing to a charge storage layer of a memory transistor. A positive voltage is applied to the drain region by using a voltage of the source region as a reference, and a voltage having a polarity in accordance with charges to be injected is applied to a gate electrode. A voltage having a voltage value between a source voltage and a drain voltage for turning on a diode made by an N-type source region and a P-type body region is applied to the body region. Then a parasitic bipolar transistor turns on, consequently, impact ionization arises on the drain side and an injection charge amount increases.