Patents by Inventor Hideki Nozaki
Hideki Nozaki has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10971095Abstract: A liquid crystal display includes source lines and gate lines, pixel electrodes, switching elements, a source driver, a gate driver, and a failure inspection circuit. The source lines and the gate lines are disposed in a lattice form. The pixel electrode is disposed in a pixel region defined by the source line and the gate line. The switching element is disposed corresponding to the pixel electrode. The source driver drives the source lines. The gate driver drives the gate lines. The failure inspection circuit is connected to the source lines or the gate lines, and performs inspection of the source lines or the gate lines. The failure inspection circuit includes monitor input signal lines, monitor output signal lines, a determination circuit that detects voltage levels of output signals from the monitor output signal lines, and an expected value comparison circuit that compares outputs from the determination circuit with expected values.Type: GrantFiled: October 26, 2017Date of Patent: April 6, 2021Assignees: PANASONIC CORPORATION, PANASONIC LIQUID CRYSTAL DISPLAY CO., LTD., PANASONIC SEMICONDUCTOR SOLUTIONS CO., LTD.Inventors: Jun Suzuki, Akihiro Yoshizawa, Hideki Nozaki, Satoshi Endou, Kenji Fukuta, Hiroaki Goto
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Publication number: 20190279585Abstract: A liquid crystal display includes source lines and gate lines, pixel electrodes, switching elements, a source driver, a gate driver, and a failure inspection circuit. The source lines and the gate lines are disposed in a lattice form. The pixel electrode is disposed in a pixel region defined by the source line and the gate line. The switching element is disposed corresponding to the pixel electrode. The source driver drives the source lines. The gate driver drives the gate lines. The failure inspection circuit is connected to the source lines or the gate lines, and performs inspection of the source lines or the gate lines. The failure inspection circuit includes monitor input signal lines, monitor output signal lines, a determination circuit that detects voltage levels of output signals from the monitor output signal lines, and an expected value comparison circuit that compares outputs from the determination circuit with expected values.Type: ApplicationFiled: October 26, 2017Publication date: September 12, 2019Applicants: Panasonic Corporation, Panasonic Liquid Crystal Display Co., Ltd.Inventors: Jun SUZUKI, Akihiro YOSHIZAWA, Hideki NOZAKI, Satoshi ENDOU, Kenji FUKUTA, Hiroaki GOTO
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Patent number: 8900962Abstract: According to one embodiment, a method is disclosed for manufacturing a semiconductor device. The method can include forming a base region and an emitter region in a front surface of a semiconductor layer. The method can include forming a first impurity implantation region by implanting first impurity of a first conductivity type into a back surface of the semiconductor layer. The method can include selectively forming a second impurity implantation region by selectively implanting second impurity of a second conductivity type into the first impurity implantation region. In addition, the method can include irradiating the first impurity implantation region and the second impurity implantation region with laser light. A peak of impurity concentration profile in a depth direction of at least one of the first impurity implantation region and the second impurity implantation region before irradiation with the laser light is adjusted to a depth of 0.05 ?m or more and 0.Type: GrantFiled: March 21, 2011Date of Patent: December 2, 2014Assignee: Kabushiki Kaisha ToshibaInventors: Daisuke Yamashita, Etsuo Hamada, Hideki Nozaki, Hironobu Shibata
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Patent number: 8301773Abstract: A server management program, a server management method, and a server management apparatus that allows an environment for providing a service corresponding to a server group for executing processing in cooperation with a server computer to be formed automatically in a standby server computer added to the server group. An image data collector collects disk image data from server computers and stores the data in an image data storage section. When an instruction to add a server computer to a server group is received, an image data addition section obtains the disk image data from the image data storage section and copies the data onto a disk of the server computer to be added. A configuration setup section sets up unique information of a mating server computer having a processing request relationship, in the server computer to be added, in accordance with processing request relationships among the server computers included in the different server groups.Type: GrantFiled: April 18, 2007Date of Patent: October 30, 2012Assignee: Fujitsu LimitedInventors: Toshihiro Mimura, Hideki Nozaki, Shuichi Chiba, Hideo Hayakawa
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Patent number: 8148240Abstract: A semiconductor wafer is prepared. The wafer has a first and a second surface opposite to each other, and has a recess portion and a rim portion. The semiconductor wafer has semiconductor elements formed on the first surface. The rim portion surrounds the recess portion. The recess portion and the rim portion are composed of the first and second surfaces. The recess portion is formed so as to recede toward the first surface. A tape is adhered to the second surface of the semiconductor wafer. At least the recess portion of the semiconductor wafer is placed on a stage. The tape is sandwiched between the recess portion and the stage. Laser beam is irradiated to the recess portion from the side of the first surface and along predetermined dicing lines. The recess portion is cut off to divide the semiconductor wafer into chips.Type: GrantFiled: August 21, 2009Date of Patent: April 3, 2012Assignee: Kabushiki Kaisha ToshibaInventors: Motoshige Kobayashi, Hideki Nozaki
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Patent number: 8099478Abstract: A program for managing applications that can replace application resources deployed over a multi-layered system with a single action. Upon receipt of a request for establishing an environment for a service, a target platform determining means consults group management data to identify server computers belonging to server groups corresponding to a plurality of functions necessary to provide the requested service. The identified server computers are chosen as target platforms on which necessary applications will be deployed to implement the functions. An application deploying means successively selects deployment data of applications required to implement the functions for the requested service and deploys each selected deployment data to the server computers chosen as the target platforms.Type: GrantFiled: April 18, 2007Date of Patent: January 17, 2012Assignee: Fujitsu LimitedInventors: Toshihiro Mimura, Hideki Nozaki, Shuichi Chiba, Hideo Hayakawa
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Publication number: 20110250728Abstract: According to one embodiment, a method is disclosed for manufacturing a semiconductor device. The method can include forming a base region and an emitter region in a front surface of a semiconductor layer. The method can include forming a first impurity implantation region by implanting first impurity of a first conductivity type into a back surface of the semiconductor layer. The method can include selectively forming a second impurity implantation region by selectively implanting second impurity of a second conductivity type into the first impurity implantation region. In addition, the method can include irradiating the first impurity implantation region and the second impurity implantation region with laser light. A peak of impurity concentration profile in a depth direction of at least one of the first impurity implantation region and the second impurity implantation region before irradiation with the laser light is adjusted to a depth of 0.05 ?m or more and 0.Type: ApplicationFiled: March 21, 2011Publication date: October 13, 2011Applicant: KABUSHIKI KAISHA TOSHIBAInventors: Daisuke Yamashita, Etsuo Hamada, Hideki Nozaki, Hironobu Shibata
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Patent number: 7975038Abstract: An application management program, application management method, and application management apparatus, which are capable of controlling the start of server computers with taking relations between multilevel applications into consideration. When receiving a request for starting provision of a service, a selection unit refers to server definition information to select a start-target server computer that should start an application, in accordance with an order of starting applications predefined based on relations in processing requests. Then, a confirmation unit refers to status information to confirm whether an associated application that should be started before the application installed on the start-target server computer selected by the selection unit has been started correctly.Type: GrantFiled: April 19, 2007Date of Patent: July 5, 2011Assignee: Fujitsu LimitedInventors: Toshihiro Mimura, Hideki Nozaki, Shuichi Chiba, Hideo Hayakawa
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Patent number: 7906416Abstract: A method for manufacturing a semiconductor device from a semiconductor wafer having a first major surface, a recess provided inside a periphery on opposite side of the first major surface and surrounded by the periphery, and a second major surface provided at bottom of the recess is provided. The method comprises: fitting into the recess a doping mask having selectively formed openings to selectively cover the second major surface with the doping mask; and selectively introducing dopant into the second major surface.Type: GrantFiled: October 12, 2007Date of Patent: March 15, 2011Assignee: Kabushiki Kaisha ToshibaInventors: Masanobu Tsuchitani, Hideki Nozaki, Motoshige Kobayashi
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Publication number: 20100203688Abstract: A semiconductor device includes: a semiconductor layer having a first major surface, a second major surface provided on opposite side of the first major surface, and a channel formation region provided in a surface portion on the first major surface side; a first main electrode provided inside a dicing street on the first major surface of the semiconductor layer; a second main electrode provided inside a dicing street on the second major surface of the semiconductor layer; and a control electrode opposed to the channel formation region across an insulating film.Type: ApplicationFiled: April 13, 2010Publication date: August 12, 2010Applicant: KABUSHIKI KAISHA TOSHIBAInventors: Motoshige Kobayashi, Hideki Nozaki, Masanobu Tsuchitani
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Patent number: 7772641Abstract: A power semiconductor device includes: a semiconductor layer having a trench extending along a first direction in a stripe configuration; a gate electrode buried in the trench for controlling a current flowing in the semiconductor layer; and a gate plug made of a material having higher electrical conductivity than the gate electrode, the gate plug having the stripe configuration and being connected to the gate electrode along the first direction. The semiconductor layer includes: a first semiconductor layer of a first conductivity type; a second semiconductor layer of a second conductivity type provided partially in an upper face of the first semiconductor layer; a third semiconductor layer of the first conductivity type provided partially on the second semiconductor layer; and a fourth semiconductor layer of the second conductivity type provided on a lower face of the first semiconductor layer.Type: GrantFiled: March 6, 2007Date of Patent: August 10, 2010Assignee: Kabushiki Kaisha ToshibaInventors: Ichiro Omura, Yoko Sakiyama, Hideki Nozaki, Atsushi Murakoshi, Masanobu Tsuchitani, Koichi Sugiyama, Tsuneo Ogura, Masakazu Yamaguchi, Tatsuo Naijo
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Publication number: 20100048000Abstract: A semiconductor wafer is prepared. The wafer has a first and a second surface opposite to each other, and has a recess portion and a rim portion. The semiconductor wafer has semiconductor elements formed on the first surface. The rim portion surrounds the recess portion. The recess portion and the rim portion are composed of the first and second surfaces. The recess portion is formed so as to recede toward the first surface. A tape is adhered to the second surface of the semiconductor wafer. At least the recess portion of the semiconductor wafer is placed on a stage. The tape is sandwiched between the recess portion and the stage. Laser beam is irradiated to the recess portion from the side of the first surface and along predetermined dicing lines. The recess portion is cut off to divide the semiconductor wafer into chips.Type: ApplicationFiled: August 21, 2009Publication date: February 25, 2010Applicant: KABUSHIKI KAISHA TOSHIBAInventors: Motoshige Kobayashi, Hideki Nozaki
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Publication number: 20080299686Abstract: A method for manufacturing a semiconductor device, includes; measuring a within-wafer distribution of a physical quantity; and etching the wafer so that the physical quantity get close to constant within the wafer. Alternatively, a method for manufacturing a semiconductor device, includes, measuring a within-wafer distribution of a physical quantity of at least one of a plurality of semiconductor layers provided in a wafer; determining a within-wafer distribution of etching amount for the at least one of the plurality of semiconductor layers based on the measured within-wafer distribution of the physical quantity; and etching the at least one of the plurality of semiconductor layers based on the determined within-wafer distribution of the etching amount so that the etching amount is locally varied within the wafer.Type: ApplicationFiled: October 12, 2007Publication date: December 4, 2008Applicant: KABUSHIKI KAISHA TOSHIBAInventors: Motoshige KOBAYASHI, Masanobu Echizenya, Shinya Takyu, Noriko Shimizu, Hideki Nozaki, Masanobu Tsuchitani
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Publication number: 20080296611Abstract: A semiconductor device includes: a semiconductor layer having a first major surface, a second major surface provided on opposite side of the first major surface, and a channel formation region provided in a surface portion on the first major surface side; a first main electrode provided inside a dicing street on the first major surface of the semiconductor layer; a second main electrode provided inside a dicing street on the second major surface of the semiconductor layer; and a control electrode opposed to the channel formation region across an insulating film.Type: ApplicationFiled: October 12, 2007Publication date: December 4, 2008Applicant: KABUSHIKI KAISHA TOSHIBAInventors: Motoshige Kobayashi, Hideki Nozaki, Masanobu Tsuchitani
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Patent number: 7373344Abstract: An apparatus for displaying system management information includes a combination storing unit that stores display pattern information that is obtained by combining, in subjective basis, system management information provided by a plurality of system management units; and a combination display unit that combines the system management information based on the display pattern stored in the combination storing unit, and displays the system management information combined.Type: GrantFiled: January 28, 2005Date of Patent: May 13, 2008Assignee: Fujitsu LimitedInventors: Hideo Sugimori, Masashi Ogawa, Hideki Nozaki, Seiya Shindo, Hiroshi Yazawa, Shinichi Doi, Taisuke Aizawa, Ken Takahashi, Gaku Sakurai
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Publication number: 20080090391Abstract: A method for manufacturing a semiconductor device from a semiconductor wafer having a first major surface, a recess provided inside a periphery on opposite side of the first major surface and surrounded by the periphery, and a second major surface provided at bottom of the recess is provided. The method comprises: fitting into the recess a doping mask having selectively formed openings to selectively cover the second major surface with the doping mask; and selectively introducing dopant into the second major surface.Type: ApplicationFiled: October 12, 2007Publication date: April 17, 2008Applicant: KABUSHIKI KAISHA TOSHIBAInventors: Masanobu TSUCHITANI, Hideki NOZAKI, Motoshige KOBAYASHI
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Publication number: 20070210350Abstract: A power semiconductor device includes: a semiconductor layer having a trench extending along a first direction in a stripe configuration; a gate electrode buried in the trench for controlling a current flowing in the semiconductor layer; and a gate plug made of a material having higher electrical conductivity than the gate electrode, the gate plug having the stripe configuration and being connected to the gate electrode along the first direction. The semiconductor layer includes: a first semiconductor layer of a first conductivity type; a second semiconductor layer of a second conductivity type provided partially in an upper face of the first semiconductor layer; a third semiconductor layer of the first conductivity type provided partially on the second semiconductor layer; and a fourth semiconductor layer of the second conductivity type provided on a lower face of the first semiconductor layer.Type: ApplicationFiled: March 6, 2007Publication date: September 13, 2007Applicant: KABUSHIKI KAISHA TOSHIBAInventors: Ichiro Omura, Yoko Sakiyama, Hideki Nozaki, Atsushi Murakoshi, Masanobu Tsuchitani, Koichi Sugiyama, Tsuneo Ogura, Masakazu Yamaguchi, Tatsuo Naijo
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Publication number: 20070204030Abstract: A server management program, a server management method, and a server management apparatus that allows an environment for providing a service corresponding to a server group for executing processing in cooperation with a server computer to be formed automatically in a standby server computer added to the server group. An image data collector collects disk image data from server computers and stores the data in an image data storage section. When an instruction to add a server computer to a server group is received, an image data addition section obtains the disk image data from the image data storage section and copies the data onto a disk of the server computer to be added. A configuration setup section sets up unique information of a mating server computer having a processing request relationship, in the server computer to be added, in accordance with processing request relationships among the server computers included in the different server groups.Type: ApplicationFiled: April 18, 2007Publication date: August 30, 2007Applicant: Fujitsu LimitedInventors: Toshihiro Mimura, Hideki Nozaki, Shuichi Chiba, Hideo Hayakawa
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Publication number: 20070198692Abstract: An application management program, application management method, and application management apparatus, which are capable of controlling the start of server computers with taking relations between multilevel applications into consideration. When receiving a request for starting provision of a service, a selection unit refers to server definition information to select a start-target server computer that should start an application, in accordance with an order of starting applications predefined based on relations in processing requests. Then, a confirmation unit refers to status information to confirm whether an associated application that should be started before the application installed on the start-target server computer selected by the selection unit has been started correctly.Type: ApplicationFiled: April 19, 2007Publication date: August 23, 2007Applicant: Fujitsu LimitedInventors: Toshihiro Mimura, Hideki Nozaki, Shuichi Chiba, Hideo Hayakawa
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Publication number: 20070192769Abstract: A program for managing applications that can replace application resources deployed over a multi-layered system with a single action. Upon receipt of a request for establishing an environment for a service, a target platform determining means consults group management data to identify server computers belonging to server groups corresponding to a plurality of functions necessary to provide the requested service. The identified server computers are chosen as target platforms on which necessary applications will be deployed to implement the functions. An application deploying means successively selects deployment data of applications required to implement the functions for the requested service and deploys each selected deployment data to the server computers chosen as the target platforms.Type: ApplicationFiled: April 18, 2007Publication date: August 16, 2007Applicant: Fujitsu LimitedInventors: Toshihiro Mimura, Hideki Nozaki, Shuichi Chiba, Hideo Hayakawa