Patents by Inventor Hideki Nozaki

Hideki Nozaki has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20060095428
    Abstract: An apparatus for displaying system management information includes a combination storing unit that stores display pattern information that is obtained by combining, in subjective basis, system management information provided by a plurality of system management units; and a combination display unit that combines the system management information based on the display pattern stored in the combination storing unit, and displays the system management information combined.
    Type: Application
    Filed: January 28, 2005
    Publication date: May 4, 2006
    Inventors: Hideo Sugimori, Masashi Ogawa, Hideki Nozaki, Seiya Shindo, Hiroshi Yazawa, Shinichi Doi, Taisuke Aizawa, Ken Takahashi, Gaku Sakurai
  • Patent number: 6649981
    Abstract: A semiconductor device comprises a first base layer for providing a PT-IGBT or IEGT structure, which includes a buffer layer and a collector layer provided in the buffer layer. A first activation rate, defined by an activated first conductivity type impurity density [cm−2] in the buffer layer due to SR analysis/a first conductivity type impurity density [cm−2] in the buffer layer due to SIMS analysis is given by 25% or more, and a second activation rate, defined by an activated second conductivity type impurity density [cm−2] in the collector layer due to SR analysis/a second conductivity type impurity density [cm−2] in the collector layer duet to SIMS analysis is given by more than 0% and 10% or less.
    Type: Grant
    Filed: March 28, 2002
    Date of Patent: November 18, 2003
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Motoshige Kobayashi, Hideki Nozaki
  • Patent number: 6562705
    Abstract: A laser heating apparatus for forming an electrode on one surface of an Si chip provided on an Si wafer, thereby producing a semiconductor element, comprises a high vacuum chamber having a light transmission window, an XY table contained in the high vacuum chamber for mounting the Si wafer thereon, heater contained in the high vacuum chamber for heating and evaporating an impurity in a solid state, and laser beam applying means for applying a laser beam to the Si chip placed on the XY table from the outside of the high vacuum chamber through the light transmission window, thereby implanting the impurity into the Si in chip and activating the implanted impurity.
    Type: Grant
    Filed: October 26, 2000
    Date of Patent: May 13, 2003
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Takashi Obara, Hideki Nozaki, Motoshige Kobayashi
  • Patent number: 6524894
    Abstract: An N+ buffer layer formed on the underside of an N− layer includes an inactive region having incompletely activated ions and an active region having highly activated ions. The carrier concentration of the active region is higher than that of the inactive region. In the inactive region, the electrical activation rate X of the ions is expressed as 1%≦X≦30%. It is thus possible to achieve a PT structure using a Raw wafer, which reduces manufacturing costs and suppresses power consumption.
    Type: Grant
    Filed: February 15, 2001
    Date of Patent: February 25, 2003
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Hideki Nozaki, Yoshiro Baba, Motoshige Kobayashi
  • Publication number: 20020140035
    Abstract: A semiconductor device comprises a first base layer for providing a PT-IGBT or IEGT structure, which includes a buffer layer and a collector layer provided in the buffer layer. A first activation rate, defined by an activated first conductivity type impurity density [cm−2] in the buffer layer due to SR analysis/a first conductivity type impurity density [cm−2] in the buffer layer due to SIMS analysis is given by 25% or more, and a second activation rate, defined by an activated second conductivity type impurity density [cm−2] in the collector layer due to SR analysis/a second conductivity type impurity density [cm−2] in the collector layer duet to SIMS analysis is given by more than 0% and 10% or less.
    Type: Application
    Filed: March 28, 2002
    Publication date: October 3, 2002
    Inventors: Motoshige Kobayashi, Hideki Nozaki
  • Publication number: 20020081784
    Abstract: An insulated gate bipolar transistor is disclosed, which comprises a first conductivity type base layer, a second conductivity type base layer and an emitter layer which are selectively formed in an upper surface of the first conductivity type base layer, a buffer layer and a collector layer which are formed on a back surface of the first conductivity type base layer. A requirement of d2/d1>1.5 is satisfied, where d1 is a depth in the buffer layer, as measured from an interface of the buffer layer and the collector layer, at which a first conductivity type impurity concentration in the buffer layer shows a peak value, and d2 is a shallowest depth in the buffer layer, as measured from the interface of the buffer layer and the collector layer, at which an activation ratio of the first conductivity type impurity in the buffer layer is a predetermined value.
    Type: Application
    Filed: December 26, 2001
    Publication date: June 27, 2002
    Inventors: Motoshige Kobayashi, Hideki Nozaki
  • Patent number: 6128644
    Abstract: A load distribution system which is capable of carrying out appropriate load distributing on a WWW system. A server status notification section provided for each server subject to management collects processing requests sent to each server. A server status management section obtains the amount of processing of each server collected by the server status notification section to manage a load status of each server. A request distribution section within a client system obtains load information on the load status of each server from the server status management section. A request relay section delivers a server selection request when a processing request is generated by the client system. In response to the server selection request, the request distribution section determines a server experiencing less load, based on the load information.
    Type: Grant
    Filed: July 20, 1998
    Date of Patent: October 3, 2000
    Assignee: Fujitsu Limited
    Inventor: Hideki Nozaki
  • Patent number: 6121635
    Abstract: A current blocking layer (7) formed immediately below a transparent electrode (9) is formed of a semiconductor layer containing Al, and a bandgap equal to or longer than the emission wavelength. Since the current blocking layer (7) is formed of such semiconductor layer, an oxide film forms on or near the surface of the current blocking layer (7) in a process of forming the transparent electrode (9) such as an ITO film containing oxygen, and the current blocking layer functions effectively. The diameter of a bonding electrode (20) is set to be smaller than that of the current blocking layer (7), thus effectively outputting the light emitted. Furthermore, the oxidized current blocking layer can have a high breakdown voltage and, hence, can be formed to have a small thickness, thus improving step coverage upon forming the transparent electrode on the current blocking layer. By inserting a thin Zn layer (8) between the transparent electrode (9) and an ohmic layer (6), the adhesion therebetween can be improved.
    Type: Grant
    Filed: April 15, 1998
    Date of Patent: September 19, 2000
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Yukio Watanabe, Ryo Saeki, Hideki Nozaki
  • Patent number: 5744828
    Abstract: A semiconductor light emitting device has a semiconductor substrate (1). On a first principal plane of the substrate, an emission layer is formed. In a predetermined region on the emission layer, a current blocking layer (10) is formed. On the current blocking layer, an excitation electrode (20) is formed. A substrate electrode (9) is formed on a second principal plane of the substrate. The excitation electrode is composed of a bonding pad (21) and a current supply electrode (22). The current blocking layer is under the bonding pad. The current blocking layer prevents a current from flowing under the bonding pad. The current supply electrode improves the light emission efficiency of the device.
    Type: Grant
    Filed: July 10, 1996
    Date of Patent: April 28, 1998
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Hideki Nozaki, Kazumi Unno, Yasuo Idei, Katsuhiko Nishitani
  • Patent number: 5639674
    Abstract: A semiconductor light-emitting element has a crystal layer formed from aluminum of a high mol ratio of 60% or greater on the light producing surface. In the semiconductor light-emitting element, a conductive crystal with aluminum of a mol ratio of 50% or less, or a conductive crystal containing no aluminum is formed on the high aluminum crystal layer.
    Type: Grant
    Filed: October 18, 1995
    Date of Patent: June 17, 1997
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Hideki Nozaki, Kazumi Unno
  • Patent number: 5586320
    Abstract: A data processing system for executing a parallel processing of programs by a plurality of computers, includes a plurality of parallel processing execution units for dividing a predetermined processing into a plurality of processings and a plurality of computers for executing a parallel processing of the parallel processing execution unit. In addition, a plurality of wait-until procedure units are provided for synchronization therewith between the plurality of computers in the case of executing a parallel processing. One computer assigns a value to a synchronous variable in the course of synchronous processing between the processors, to vary the value of the synchronous variable regularly, and another computer is adapted to suspend operations using a wait-until procedure until a value of a synchronous variable surpasses a predetermined value. Thus, the invention reduces an overhead time of the synchronous processing by effectively executing a parallel processing of programs.
    Type: Grant
    Filed: November 4, 1994
    Date of Patent: December 17, 1996
    Assignee: Fujitsu Limited
    Inventors: Koh-Ichiro Hotta, Hiroshi Nagakura, Eiji Yamanaka, Hideki Nozaki
  • Patent number: 5488235
    Abstract: A semiconductor light-emitting element has a crystal layer formed from aluminum of a high mol ratio of 60% or greater on the light producing surface. In the semiconductor light-emitting element, a conductive crystal with aluminum of a mol ratio of 50% or less, or a conductive crystal containing no aluminum is formed on the high aluminum crystal layer.
    Type: Grant
    Filed: June 1, 1995
    Date of Patent: January 30, 1996
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Hideki Nozaki, Kazumi Unno