Patents by Inventor Hideki Okumura
Hideki Okumura has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 9865680Abstract: A semiconductor device includes a first semiconductor region of a first conductivity type on a first electrode and a second semiconductor region of the first conductivity type on a central portion of the first semiconductor region. The second region has a carrier concentration less than a carrier concentration of the first region. A third semiconductor region of a second conductivity type is on the second semiconductor region. A first insulating portion covers a peripheral surface of the second semiconductor region and a peripheral surface of the third semiconductor region. A second insulating portion is spaced from the first insulating portion in a lateral direction. A void space is between the first and second insulating portions. A third insulating portion is on the third semiconductor region and spans and covers the void space. A second electrode is on the third semiconductor region and the third insulating portion.Type: GrantFiled: August 29, 2016Date of Patent: January 9, 2018Assignee: Kabushiki Kaisha ToshibaInventors: Hideki Okumura, Takuya Yamaguchi, Masanobu Tsuchitani, Sadayuki Jimbo
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Publication number: 20170355197Abstract: A liquid holding unit supplies liquid to a liquid ejector of a liquid ejection device. The liquid holding unit includes a liquid holder, an inlet, a plug, a shaft, and an engagement portion. The liquid holder holds the liquid. The housing accommodates the liquid holder. The inlet is used to fill the liquid holder with the liquid. The plug opens and closes the inlet and includes an elastically deformable plug body that covers the inlet and a holding member that holds the plug body and has higher rigidity than the plug body. The shaft is arranged on one of the housing and the plug. The plug is pivotal about the shaft. The engagement portion arranged on the other one of the housing and the plug and engaged with the shaft.Type: ApplicationFiled: May 30, 2017Publication date: December 14, 2017Inventors: Shoma KUDO, Naomi KIMURA, Hideki OKUMURA, Motoyoshi SHIROTORI, Kazuo OTSUKA, Masafumi FURUYAMA
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Publication number: 20170263703Abstract: A semiconductor device includes a first semiconductor region of a first conductivity type on a first electrode and a second semiconductor region of the first conductivity type on a central portion of the first semiconductor region. The second region has a carrier concentration less than a carrier concentration of the first region. A third semiconductor region of a second conductivity type is on the second semiconductor region. A first insulating portion covers a peripheral surface of the second semiconductor region and a peripheral surface of the third semiconductor region. A second insulating portion is spaced from the first insulating portion in a lateral direction. A void space is between the first and second insulating portions. A third insulating portion is on the third semiconductor region and spans and covers the void space. A second electrode is on the third semiconductor region and the third insulating portion.Type: ApplicationFiled: August 29, 2016Publication date: September 14, 2017Inventors: Hideki OKUMURA, Takuya YAMAGUCHI, Masanobu TSUCHITANI, Sadayuki JIMBO
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Patent number: 9761711Abstract: A semiconductor device includes a first electrode, a second electrode, a first semiconductor region of a first conductivity type that is between the first electrode and the second electrode. A second semiconductor region is adjacent to the first semiconductor region along a first direction and includes a second conductivity type material. A first insulating region is provided within the second semiconductor region. A third electrode is provided on the first semiconductor region via a second insulating region.Type: GrantFiled: March 3, 2016Date of Patent: September 12, 2017Assignee: Kabushiki Kaisha ToshibaInventors: Kankichi Ito, Hideki Okumura
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Publication number: 20170077298Abstract: A semiconductor device includes a first electrode, a second electrode, a first semiconductor region of a first conductivity type that is between the first electrode and the second electrode. A second semiconductor region is adjacent to the first semiconductor region along a first direction and includes a second conductivity type material. A first insulating region is provided within the second semiconductor region. A third electrode is provided on the first semiconductor region via a second insulating region.Type: ApplicationFiled: March 3, 2016Publication date: March 16, 2017Inventors: Kankichi ITO, Hideki OKUMURA
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Publication number: 20170069714Abstract: A semiconductor device includes a first semiconductor region of a first conductivity type, a second semiconductor region of the first conductivity type, a third semiconductor region of the second conductivity type, and an insulating portion. The second semiconductor region is provided on the first semiconductor region. The third semiconductor region is provided on the second semiconductor region. The insulating portion is located in a vicinity of, and contacts, the second semiconductor region and the third semiconductor region, and the insulating portion includes a plurality of voids therein, the plurality of voids extending around the second semiconductor region.Type: ApplicationFiled: August 30, 2016Publication date: March 9, 2017Inventors: Masanobu TSUCHITANI, Hideki OKUMURA, Sadayuki JIMBO, Takuya YAMAGUCHI
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Publication number: 20160276430Abstract: According to an embodiment, a semiconductor device includes a first semiconductor region of a first conductivity type, a second semiconductor region of a second conductivity type, a first insulating layer, and a first insulating region. The second semiconductor region is provided on the first semiconductor region. The first insulating layer is provided around at least a portion of the first semiconductor region and at least a portion of the second semiconductor region. The first insulating layer contacts the second semiconductor region. The first insulating region is provided around at least a portion of the first insulating layer.Type: ApplicationFiled: September 7, 2015Publication date: September 22, 2016Inventors: Hideki Okumura, Masanobu Tsuchitani, Hiroto Misawa, Akira Ezaki, Tatsuya Shiraishi
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Publication number: 20160079374Abstract: A manufacturing method of a semiconductor device includes forming a first electrode on a lower portion of a trench that is formed on a semiconductor layer and having a first insulating film between the first electrode and the semiconductor layer; forming a second insulating film that covers an inner surface of an upper portion of the trench, forming a resist film that extends into the upper portion of the trench on the second insulating film, removing the second insulating film between the resist film and a side wall of the trench to leave a portion of the second insulating film on the first electrode, forming a third insulating film on a side wall of an upper portion of the trench, and forming a second electrode on the first electrode in an inner portion of the second insulating film.Type: ApplicationFiled: February 17, 2015Publication date: March 17, 2016Inventor: HIDEKI OKUMURA
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Publication number: 20160071940Abstract: According to an embodiment, a semiconductor device includes a first semiconductor layer of a first conductivity type, a first electrode over the first semiconductor layer, second and third electrodes extending in the first semiconductor layer in a direction from the first electrode to the first semiconductor layer, a second semiconductor layer of a second conductivity type on the first semiconductor layer. The device further includes third semiconductor layers of the second conductivity type between the first semiconductor layer and each of the second electrode and the third electrode, first insulating films between one of the third semiconductor layers and the second electrode and between the other of the third semiconductor layers and the third electrode, a fourth semiconductor layer of the first conductivity type on the second semiconductor layer, and a fourth electrode extending through the fourth semiconductor layer and the second semiconductor layer to the first semiconductor layer.Type: ApplicationFiled: March 5, 2015Publication date: March 10, 2016Inventor: Hideki Okumura
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Patent number: 9142667Abstract: According to one embodiment, a method for manufacturing a semiconductor device includes: forming a plurality of trenches; forming a gate insulating film; burying a gate electrode; burying an insulating member; projecting the insulating member; forming a base layer; forming a mask film; forming a first semiconductor layer; forming a carrier ejection layer; forming a first electrode; and forming a second electrode. The projecting includes projecting the insulating member from the upper surface of the semiconductor substrate by removing an upper layer portion of the semiconductor substrate. The mask film is formed so as to cover the projected insulating member. The forming the first semiconductor layer includes forming a first semiconductor layer of the first conductivity type in an upper layer portion of the base layer by doping the base layer with impurity, the upper layer portion having a lower surface below an upper end of the gate electrode.Type: GrantFiled: September 12, 2014Date of Patent: September 22, 2015Assignee: Kabushiki Kaisha ToshibaInventors: Hideki Okumura, Hiroto Misawa, Takahiro Kawano
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Publication number: 20150263162Abstract: In one embodiment, a semiconductor device includes first, second, third, fourth, fifth and sixth electrodes extending in a first direction, the third and fourth electrodes being provided to sandwich the first electrode, the fifth and sixth electrodes being provided to sandwich the second electrode, the first, second, fifth and sixth electrodes being electrically connected with one another, and the third and fourth electrodes being electrically connected with each other and electrically independent from the first, second, fifth and sixth electrodes. The device further includes a semiconductor layer provided between one of the third and fourth electrodes and one of the fifth and sixth electrodes. The device further includes a first interconnect provided on the second, fifth and sixth electrodes and on the semiconductor layer.Type: ApplicationFiled: September 10, 2014Publication date: September 17, 2015Inventors: Toshifumi Nishiguchi, Hideki Okumura
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Publication number: 20150179764Abstract: A semiconductor device includes first to fourth semiconductor layers, a gate electrode, a field plate electrode, an insulating film, first and second main electrodes, and an insulating section. The second semiconductor layer has the first conductivity type and is provided on the first semiconductor layer. The third semiconductor layer has a second conductivity type and is provided on the second semiconductor layer. A concentration of impurity of the first conductivity type included in the third semiconductor layer is lower than the concentration of impurity of the first conductivity type included in the second semiconductor layer. The fourth semiconductor layer is provided on the third semiconductor layer. The gate electrode extends from the fourth semiconductor layer toward the second semiconductor layer. The field plate electrode is provided below the gate electrode.Type: ApplicationFiled: March 5, 2015Publication date: June 25, 2015Applicant: KABUSHIKI KAISHA TOSHIBAInventor: Hideki OKUMURA
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Publication number: 20150069592Abstract: In one embodiment, a semiconductor device includes a lead frame including an island portion and a terminal portion separated from the island portion. The device further includes a semiconductor chip mounted on the island portion and including an electrode. The device further includes an insulating layer disposed on the semiconductor chip and having an opening to expose at least a part of the electrode. The device further includes a connector covering the electrode exposed through the opening and electrically connecting the electrode and the terminal portion.Type: ApplicationFiled: March 6, 2014Publication date: March 12, 2015Applicant: Kabushiki Kaisha ToshibaInventors: Koji Tamura, Nobuyuki Sato, Nobuhiro Shingai, Shinya Ozawa, Takeru Matsuoka, Hideki Okumura
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Publication number: 20150069598Abstract: In one embodiment, a heat dissipation connector mounted on a semiconductor chip and sealed up with a molding resin along with the semiconductor chip and a lead frame includes a heat dissipation portion configured to have a block shape, and have an upper face exposed out of the molding resin. The connector further includes a connecting portion configured to extend from a first side face of the heat dissipation portion, and electrically connect an electrode arranged on the semiconductor chip to the lead frame. The heat dissipation portion and the connecting portion are integrally made of the same metal sheet.Type: ApplicationFiled: March 6, 2014Publication date: March 12, 2015Applicant: KABUSHIKI KAISHA TOSHIBAInventors: Koji Tamura, Nobuyuki Sato, Nobuhiro Shingai, Shinya Ozawa, Takeru Matsuoka, Hideki Okumura
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Publication number: 20150028413Abstract: According to one embodiment, a method for manufacturing a semiconductor device includes: forming a plurality of trenches; forming a gate insulating film; burying a gate electrode; burying an insulating member; projecting the insulating member; forming a base layer; forming a mask film; forming a first semiconductor layer; forming a carrier ejection layer; forming a first electrode; and forming a second electrode. The projecting includes projecting the insulating member from the upper surface of the semiconductor substrate by removing an upper layer portion of the semiconductor substrate. The mask film is formed so as to cover the projected insulating member. The forming the first semiconductor layer includes forming a first semiconductor layer of the first conductivity type in an upper layer portion of the base layer by doping the base layer with impurity, the upper layer portion having a lower surface below an upper end of the gate electrode.Type: ApplicationFiled: September 12, 2014Publication date: January 29, 2015Inventors: Hideki OKUMURA, Hiroto MISAWA, Takahiro KAWANO
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Patent number: 8890237Abstract: A power semiconductor device according to one embodiment includes a first electrode, a semiconductor substrate provided on the first electrode, and an insulating member. A terminal trench is made in the upper surface of the semiconductor substrate in a region including a boundary between a cell region and a terminal region. The semiconductor substrate includes a first portion of a first conductivity type and connected to the first electrode, a second portion of the first conductivity type, a third portion of a second conductivity type provided on the second portion in the cell region and connected to the second electrode, and a fourth portion of the first conductivity type selectively provided on the third portion and connected to the second electrode. The insulating member is disposed between the third portion and the second portion in a direction from the cell region toward the terminal region.Type: GrantFiled: March 13, 2012Date of Patent: November 18, 2014Assignee: Kabushiki Kaisha ToshibaInventors: Takahiro Kawano, Hideki Okumura
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Patent number: 8859365Abstract: According to one embodiment, a method for manufacturing a semiconductor device includes: forming a plurality of trenches; forming a gate insulating film; burying a gate electrode; burying an insulating member; projecting the insulating member; forming a base layer; forming a mask film; forming a first semiconductor layer; forming a carrier ejection layer; forming a first electrode; and forming a second electrode. The projecting includes projecting the insulating member from the upper surface of the semiconductor substrate by removing an upper layer portion of the semiconductor substrate. The mask film is formed so as to cover the projected insulating member. The forming the first semiconductor layer includes forming a first semiconductor layer of the first conductivity type in an upper layer portion of the base layer by doping the base layer with impurity, the upper layer portion having a lower surface below an upper end of the gate electrode.Type: GrantFiled: March 3, 2014Date of Patent: October 14, 2014Assignee: Kabushiki Kaisha ToshibaInventors: Hideki Okumura, Hiroto Misawa, Takahiro Kawano
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Publication number: 20140179075Abstract: According to one embodiment, a method for manufacturing a semiconductor device includes: forming a plurality of trenches; forming a gate insulating film; burying a gate electrode; burying an insulating member; projecting the insulating member; forming a base layer; forming a mask film; forming a first semiconductor layer; forming a carrier ejection layer; forming a first electrode; and forming a second electrode. The projecting includes projecting the insulating member from the upper surface of the semiconductor substrate by removing an upper layer portion of the semiconductor substrate. The mask film is formed so as to cover the projected insulating member. The forming the first semiconductor layer includes forming a first semiconductor layer of the first conductivity type in an upper layer portion of the base layer by doping the base layer with impurity, the upper layer portion having a lower surface below an upper end of the gate electrode.Type: ApplicationFiled: March 3, 2014Publication date: June 26, 2014Applicant: KABUSHIKI KAISHA TOSHIBAInventors: Hideki OKUMURA, Hiroto MISAWA, Takahiro KAWANO
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Patent number: 8710582Abstract: According to one embodiment, a method for manufacturing a semiconductor device includes: forming a plurality of trenches; forming a gate insulating film; burying a gate electrode; burying an insulating member; projecting the insulating member; forming a base layer; forming a mask film; forming a first semiconductor layer; forming a carrier ejection layer; forming a first electrode; and forming a second electrode. The projecting includes projecting the insulating member from the upper surface of the semiconductor substrate by removing an upper layer portion of the semiconductor substrate. The mask film is formed so as to cover the projected insulating member. The forming the first semiconductor layer includes forming a first semiconductor layer of the first conductivity type in an upper layer portion of the base layer by doping the base layer with impurity, the upper layer portion having a lower surface below an upper end of the gate electrode.Type: GrantFiled: March 14, 2012Date of Patent: April 29, 2014Assignee: Kabushiki Kaisha ToshibaInventors: Hideki Okumura, Hiroto Misawa, Takahiro Kawano
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Publication number: 20140077292Abstract: According to one embodiment, a semiconductor device includes a semiconductor substrate including a drain layer of a first conductivity type and a base layer of a second conductivity type provided on the drain layer, a gate electrode including a first portion formed in the semiconductor substrate, a gate insulating layer provided between the gate electrode and the semiconductor substrate, an upper insulating layer formed on the gate electrode, a source layer of the first conductivity type that is provided on a sidewall of the upper insulating layer and whose width increases towards the base layer, and a source electrode provided on the source layer.Type: ApplicationFiled: March 22, 2013Publication date: March 20, 2014Inventors: Takuya NOGAMI, Hideki OKUMURA, Takahiro KAWANO