Abstract: A semiconductor device comprises: a semiconductor layer of a first conductivity type; a first semiconductor pillar layer of the first conductivity type; a second semiconductor pillar layer of a second conductivity type; a third semiconductor pillar layer of the first conductivity type; a forth semiconductor pillar layer of the second conductivity type; a fifth semiconductor pillar layer of the first conductivity type provided on the major surface of the semiconductor layer; a first semiconductor base layer of the second conductivity type provided on the second semiconductor pillar layer; a second semiconductor base layer of the second conductivity type provided on the forth semiconductor pillar layer; first semiconductor region of the first conductivity type selectively provided on a surface of the first semiconductor base layer; second semiconductor region of the first conductivity type selectively provided on a surface of the second semiconductor base layer; gate insulating film provided on the first semico

Abstract: There is provided a semiconductor device including a semiconductor substrate with a trench, and a particulate insulating layer filling at least a lower portion of the trench and containing insulating particles. The semiconductor device may further include a reflowable dielectric layer covering an upper surface of the particulate insulating layer, the insulating particles being stable at the melting point or the softening point of the reflowable dielectric layer.

Abstract: In a gas permeability measurement method according to the present invention, an isotopic gas having a mass number different to that of a target gas for measurement is introduced into one of two spaces divided by a test piece, and the isotopic gas having permeated the test piece and transferred to another space is detected to thereby measure the permeability of the target gas.

Abstract: A semiconductor device which comprises a semiconductor substrate, semiconductor pillar regions each having first and second semiconductor pillar portions, the second semiconductor pillar portion being sandwiched by the first semiconductor pillar portions, a base layer formed in the second semiconductor pillar portion, a source diffusion layer formed in the base layer, a gate insulating film formed on a portion of the base layer, a gate electrode formed on the gate insulating film, and isolation regions which isolates the semiconductor pillar regions from each other and are formed in trenches between the semiconductor pillar regions, wherein each of the isolation regions comprises an oxide film formed on an inner surface of the trench and a nitride film formed on the oxide film, the nitride film being filled in the trench, and a film thickness ratio of the oxide film and the nitride film is in a range of 2:1 to 5:1.

Abstract: There is provided a semiconductor device including a semiconductor substrate with a trench, and a particulate insulating layer filling at least a lower portion of the trench and containing insulating particles. The semiconductor device may further include a reflowable dielectric layer covering an upper surface of the particulate insulating layer, the insulating particles being stable at the melting point or the softening point of the reflowable dielectric layer.

Abstract: A semiconductor device which comprises a semiconductor substrate, semiconductor pillar regions each having first and second semiconductor pillar portions, the second semiconductor pillar portion being sandwiched by the first semiconductor pillar portions, a base layer formed in the second semiconductor pillar portion, a source diffusion layer formed in the base layer, a gate insulating film formed on a portion of the base layer, a gate electrode formed on the gate insulating film, and isolation regions which isolates the semiconductor pillar regions from each other and are formed in trenches between the semiconductor pillar regions, wherein each of the isolation regions comprises an oxide film formed on an inner surface of the trench and a nitride film formed on the oxide film, the nitride film being filled in the trench, and a film thickness ratio of the oxide film and the nitride film is in a range of 2:1 to 5:1.

Abstract: A semiconductor device includes a diffusion area formed in a semiconductor layer of a first conductive type. The diffusion area comprises first and second impurity diffusion areas of the first and second conductive types, respectively. The diffusion area has a first and second areas which are defined by an impurity concentration of the first and second impurity diffusion areas. A junction between the first and second area is formed in a portion in which the first and second impurity diffusion areas overlap each other. A period of the impurity concentration, in a planar direction of the semiconductor layer, of the first or second area is smaller than the maximum width, in the planar direction of the semiconductor layer, of the first and second impurity diffusion areas constituting the first or second area.

Abstract: A cap member (10) which is brought into contact with a nozzle forming surface of a recording head (15) to seal up the nozzle forming surface, and a wiping member (11) which may be brought into sliding contact with the nozzle forming surface of the recording head (15) are disposed on a cap holder (31). With progress of a cleaning operation in which ink is placed under a negative pressure, and sucked and discharged from the recording head, a cap retaining member (50) is moved upward and placed to a set state, whereby blocking the slanting and downward movement of the cap member (10). Then, the wiping member (11) located on the cap holder (31) slides on the nozzle forming surface to wipe the nozzle forming surface. To a flushing operation, the cap retaining member (50) is moved downward and placed to a reset state. In this state, the wiping member (11) does not slide on the nozzle forming surface.

Abstract: A semiconductor device comprises a drain region formed on the reverse side of a semiconductor substrate, a base region formed on the drain region and having parts partially exposed at plural positions on a principal plane of the substrate, a source region which has one plane in contact with the base region and the other plane exposed on the principal plane of the substrate, a gate insulating film formed only on a wall of a trench, which is formed in the substrate to reach the drain region, a gate electrode formed so as to be embedded in the trench and a top surface thereof is situated above the junction plane of the source and base regions and at a position lower than the principal plane of the substrate, and an insulating film embedded above the gate electrode in the trench.

Abstract: A cap member (10) which is brought into contact with a nozzle forming surface of a recording head (15) to seal up the nozzle forming surface, and a wiping member (11) which may be brought into sliding contact with the nozzle forming surface of the recording head (15) are disposed on a cap holder (31). With progress of a cleaning operation in which ink is placed under a negative pressure, and sucked and discharged from the recording head, a cap retaining member (50) is moved upward and placed to a set state, whereby blocking the slanting and downward movement of the cap member (10). Then, the wiping member (11) located on the cap holder (31) slides on the nozzle forming surface to wipe the nozzle forming surface. To a flushing operation, the cap retaining member (50) is moved downward and placed to a reset state. In this state, the wiping member (11) does not slide on the nozzle forming surface.

Abstract: An electronic field reduction in a corner of a trench section of a semiconductor is achieved by forming a p-type base region in a source area of an n-type drain region, and both an n-type source region and a gate leading region are formed in a surface area of the p-type base region separately from each other. A trench section is formed in both the source region and gate leading region to reach the drain region. Polysilicon is formed in the trench section and on the surface of a semiconductor substrate with a gate insulation film interposed therebetween and then thermally treated. An interlayer insulation film is deposited on the entire surface of the semiconductor substrate, and then contact holes reaching the gate leading region and the source and base regions in the peripheral portion of the trench section in the source region are formed. A source/base electrode which contacts both the source and base regions through one of the contact holes is formed.

Abstract: A semiconductor device is characterized in that source electrode contact regions, each of which is formed of a first conductivity type source layer and a second conductivity type base layer in a surface of a semiconductor surface, are formed at respective intersectional points of a diagonally-arranged lattice, and in that a trench having a gate electrode buried therein is formed so as to snake through the contact regions alternately. By virtue of the structure, the trench arrangement and source/base simultaneous contact quality are improved, to thereby increase a trench density (channel density) per unit area.

Abstract: The most distinctive feature of the present invention lies in that a warp and crystal defects can be prevented from occurring and a processing margin for forming an isolation groove can be improved in an intelligent power device including a power element section and an IC control section within one chip. A bonded wafer is obtained by bonding an active-layer substrate and a supporting substrate with an epitaxially grown silicon layer interposed therebetween so as to cover an oxide film selectively formed at the interface of the active-layer substrate. Isolation trenches are then formed in the bonded wafer to such a depth as to reach the oxide film from the element forming surface of the active-layer substrate. Thus, an IC controller is formed within a dielectric isolation region surrounded with the isolation trenches and the oxide film and accordingly the IC controller can effectively be isolated by a dielectric.

Abstract: A magnetic recording medium including a non-magnetic polymeric support and a magnetic layer on the non-magnetic polymeric support. The magnetic layer is positioned to be in contact with a record/playback head and includes ferromagnetic powder, abrasive material and binder resin, with at least 40 parts by weight of the abrasive material per 100 parts by weight of the ferromagnetic powder. The ferromagnetic powder has a saturation magnetization .sigma.s of 80 emu/g or more and long axis length of 0.25 .mu.m or less.

Abstract: A tape cassette has a pair of reels each including a reel hub, with each hub having an anchor groove defined in an outer peripheral surface thereof so as to extend in a lengthwise direction thereof. A generally elongated clamping piece is received within the anchor groove and has a predetermined width as measured circumferentially of the reel hub. A tape medium includes a length of magnetic recording tape having opposite ends, and a leader tape connected with each of the opposite ends of the length of magnetic recording tape by of a splicing tape of a predetermined length. One end of the leader tape remote from the length of magnetic recording tape is received within the reel hub and anchored to the reel hub with the clamping piece snapped into the anchor groove. The splicing tape is, when the tape medium is wound around the reel hub, positioned immediately radially outwardly of and encompassing the predetermined width of the clamping piece.