Patents by Inventor Hideki Satake

Hideki Satake has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20070212829
    Abstract: A method of manufacturing an MIS semiconductor device includes forming a high dielectric film on a main surface of a semiconductor substrate, forming a silicon film on the high dielectric film, annealing the semiconductor substrate after the silicon film is formed, processing the high dielectric film and the silicon film into a gate pattern after the semiconductor substrate is annealed, to form a gate insulating film and a gate electrode, and forming source and drain regions on the main surface of the semiconductor substrate using the gate electrode as a mask.
    Type: Application
    Filed: March 8, 2007
    Publication date: September 13, 2007
    Inventors: Masashi Takahashi, Toshihide Nabatame, Hideki Satake
  • Patent number: 7268411
    Abstract: A capacitor includes a first electrode, an insulating film and a second electrode. The insulating film includes n layers of barrier layers each consisting of a material having a bandgap larger than a first bandgap and having a relative permittivity smaller than a first relative permittivity, and (n?1) layers of well layers each consisting of a material having a bandgap smaller than the first bandgap and having a relative permittivity larger than the first relative permittivity. The barrier layers and the well layers are stacked by turns. Discrete energy levels are formed in each of the well layers by a quantum effect. Thicknesses of the n layers of the barrier layers are not smaller than 2.5 angstroms. A thickness dm (angstrom) and a relative permittivity ?m of an m-th barrier layer satisfying the condition: 2.5 >(d1/?1+d2/?2+. . . +dn/?n).
    Type: Grant
    Filed: February 6, 2006
    Date of Patent: September 11, 2007
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Tatsuo Shimizu, Hideki Satake
  • Patent number: 7208802
    Abstract: An insulating film includes a first barrier layer, a well layer provided on the first barrier layer, a second barrier layer provided on the well layer. The first barrier layer consists of a material having a first bandgap and a first relative permittivity. The well layer consists of a material having a second bandgap smaller than the first bandgap and having a second relative permittivity larger than first relative permittivity. The second barrier layer consists of a material having a third bandgap larger than the second bandgap and having a third relative perminivity smaller than second relative permittivity. Each of the first and second barrier layers has a thickness not smaller than 2.5 angstroms, and 2.5>(d1/?1+d2/?2) is satisfied where d1 and d2 (angstrom) are the thicknesses of the first and second barrier layers, respectively, ?1 is the first relative permittivity, and ?2 is the third permittivity.
    Type: Grant
    Filed: February 6, 2006
    Date of Patent: April 24, 2007
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Tatsuo Shimizu, Hideki Satake
  • Patent number: 7208360
    Abstract: A semiconductor device is proposed which includes: a semiconductor substrate of a first conductivity type; a channel region formed at a surface of the semiconductor substrate; source and drain regions of a second conductivity type formed at both sides of the channel region in the semiconductor substrate; an insulating layer covering the channel region; and a gate electrode formed on the insulating layer, the insulating layer containing impurity atoms in such a manner that a concentration thereof is non-uniformly distributed along a surface parallel to the semiconductor substrate.
    Type: Grant
    Filed: March 22, 2006
    Date of Patent: April 24, 2007
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Hideki Satake
  • Publication number: 20060237837
    Abstract: There is provided a field effect transistor including: a first insulating film formed on a semiconductor substrate, and including at least a metal oxide having a crystallinity and different in a lattice distance of a crystal on an interface from the semiconductor substrate; a convex channel region formed above the first insulating film, and different in the lattice distance from the semiconductor substrate; a source region and a drain region formed above the first insulating film on side surfaces of the channel region, respectively; a second insulating film formed right above the channel region; a gate insulating film formed on a side surface of the channel region different from the side surfaces of the channel region on which the source region and the drain regions are formed; and a gate electrode formed through the gate insulating film on at least the side surface of the channel region different from the side surfaces of the channel region on which the source region and the drain region are formed.
    Type: Application
    Filed: June 22, 2006
    Publication date: October 26, 2006
    Applicant: Kabushiki Kaisha Toshiba
    Inventors: Daisuke Matsushita, Yukie Nishikawa, Hideki Satake, Noburu Fukushima
  • Patent number: 7109103
    Abstract: A semiconductor device including a silicon substrate, a gate insulator film formed on the silicon substrate and including silicon, deuterium, and at least one of oxygen and nitrogen, and a gate electrode formed on the gate insulator film wherein a deuterium concentration in a vicinity of an interface of the gate insulator film with the gate electrode is at least 1×1017 cm?3, and a deuterium concentration in a vicinity of an interface of the gate insulator film with the silicon substrate is higher than the deuterium concentration in the vicinity of the interface of the gate insulation film with the gate electrode.
    Type: Grant
    Filed: June 22, 2004
    Date of Patent: September 19, 2006
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Yuichiro Mitani, Hideki Satake
  • Patent number: 7091561
    Abstract: There is provided a field effect transistor including: a first insulating film formed on a semiconductor substrate, and including at least a metal oxide having a crystallinity and different in a lattice distance of a crystal on an interface from the semiconductor substrate; a convex channel region formed above the first insulating film, and different in the lattice distance from the semiconductor substrate; a source region and a drain region formed above the first insulating film on side surfaces of the channel region, respectively; a second insulating film formed right above the channel region; a gate insulating film formed on a side surface of the channel region different from the side surfaces of the channel region on which the source region and the drain regions are formed; and a gate electrode formed through the gate insulating film on at least the side surface of the channel region different from the side surfaces of the channel region on which the source region and the drain region are formed.
    Type: Grant
    Filed: June 9, 2004
    Date of Patent: August 15, 2006
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Daisuke Matsushita, Yukie Nishikawa, Hideki Satake, Noburu Fukushima
  • Publication number: 20060160289
    Abstract: A semiconductor device is proposed which includes: a semiconductor substrate of a first conductivity type; a channel region formed at a surface of the semiconductor substrate; source and drain regions of a second conductivity type formed at both sides of the channel region in the semiconductor substrate; an insulating layer covering the channel region; and a gate electrode formed on the insulating layer, the insulating layer containing impurity atoms in such a manner that a concentration thereof is non-uniformly distributed along a surface parallel to the semiconductor substrate.
    Type: Application
    Filed: March 22, 2006
    Publication date: July 20, 2006
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventor: Hideki Satake
  • Publication number: 20060138508
    Abstract: An insulating film comprising: a first barrier layer;a well layer provided; and a second barrier layer is proposed. The first barrier layer consists of a material having a first bandgap and a first relative permittivity. The well layer is provided on the first. barrier layer, and consists of a material having a second bandgap smaller than the first bandgap and having a second relative permittivity larger than first relative permittivity. Discrete energy levels are formed in the well layer by a quantum effect. The second barrier layer is provided on the well layer, and consists of a material having a third bandgap larger than the second bandgap and having a third relative permittivity smaller than second relative permittivity.
    Type: Application
    Filed: February 6, 2006
    Publication date: June 29, 2006
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Tatsuo Shimizu, Hideki Satake
  • Publication number: 20060131674
    Abstract: An insulating film comprising: a first barrier layer; a well layer provided; and a second barrier layer is proposed. The first barrier layer consists of a material having a first bandgap and a first relative permittivity. The well layer is provided on the first barrier layer, and consists of a material having a second bandgap smaller than the first bandgap and having a second relative permittivity larger than first relative permittivity. Discrete energy levels are formed in the well layer by a quantum effect. The second barrier layer is provided on the well layer, and consists of a material having a third bandgap larger than the second bandgap and having a third relative permittivity smaller than second relative permittivity.
    Type: Application
    Filed: February 6, 2006
    Publication date: June 22, 2006
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Tatsuo Shimizu, Hideki Satake
  • Publication number: 20060131673
    Abstract: An insulating film comprising: a first barrier layer; a well layer provided; and a second barrier layer is proposed. The first barrier layer consists of a material having a first bandgap and a first relative permittivity. The well layer is provided on the first barrier layer, and consists of a material having a second bandgap smaller than the first bandgap and having a second relative permittivity larger than first relative permittivity. Discrete energy levels are formed in the well layer by a quantum effect. The second barrier layer is provided on the well layer, and consists of a material having a third bandgap larger than the second bandgap and having a third relative permittivity smaller than second relative permittivity.
    Type: Application
    Filed: February 6, 2006
    Publication date: June 22, 2006
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Tatsuo Shimizu, Hideki Satake
  • Patent number: 7026693
    Abstract: An insulating film comprising: a first barrier layer;a well layer provided; and a second barrier layer is proposed. The first barrier layer consists of a material having a first bandgap and a first relative permittivity. The well layer is provided on the first barrier layer, and consists of a material having a second bandgap smaller than the first bandgap and having a second relative permittivity larger than first relative permittivity. Discrete energy levels are formed in the well layer by a quantum effect. The second barrier layer is provided on the well layer, and consists of a material having a third bandgap larger than the second bandgap and having a third relative permittivity smaller than second relative permittivity.
    Type: Grant
    Filed: September 30, 2003
    Date of Patent: April 11, 2006
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Tatsuo Shimizu, Hideki Satake
  • Publication number: 20050215035
    Abstract: Provided is a semiconductor device including a silicon substrate, a gate insulator disposed on the silicon substrate and containing a metal oxide, a gate electrode disposed on the gate insulator, and a sidewall insulating film disposed on a side of the gate insulator and the gate electrode and containing aluminum, silicon, oxygen and nitrogen.
    Type: Application
    Filed: May 25, 2005
    Publication date: September 29, 2005
    Inventors: Takeshi Yamaguchi, Hideki Satake, Noburu Fukushima
  • Patent number: 6930335
    Abstract: Provided is a semiconductor device including a silicon substrate, a gate insulator disposed on the silicon substrate and containing a metal oxide, a gate electrode disposed on the gate insulator, and a sidewall insulating film disposed on a side of the gate insulator and the gate electrode and containing aluminum, silicon, oxygen and nitrogen.
    Type: Grant
    Filed: March 27, 2003
    Date of Patent: August 16, 2005
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Takeshi Yamaguchi, Hideki Satake, Noburu Fukushima
  • Patent number: 6914312
    Abstract: A MIS type field effect transistor including gate dielectrics having a rare-earth metal oxynitride layer with a high dielectric constant, which can maintain good interface characteristics, can be provided. A field effect transistor according to one aspect of this invention includes a gate dielectric having a substantially crystalline rare-earth metal oxynitride layer containing one or more metals selected from rare-earth metals, oxygen, and nitrogen. The rare-earth metal oxynitride layer contacts a predetermined region of a Si semiconductor substrate, and the nitrogen exists at the interface between the rare-earth metal oxynitride layer and the Si semiconductor substrate, and in the bulk of the rare-earth metal oxynitride. The transistor further includes a gate electrode formed on the gate dielectrics and source and drain regions, one being formed at one side of the gate electrode and the other being formed at the other side of the gate electrode in the Si semiconductor substrate.
    Type: Grant
    Filed: March 26, 2003
    Date of Patent: July 5, 2005
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Yukie Nishikawa, Noburu Fukushima, Takeshi Yamaguchi, Hideki Satake
  • Patent number: 6891238
    Abstract: A semiconductor device including a silicon substrate, a gate insulator film formed on the silicon substrate and including silicon, deuterium, and at least one of oxygen and nitrogen, and a gate electrode formed on the gate insulator film wherein a deuterium concentration in a vicinity of an interface of the gate insulator film with the gate electrode is at least 1×107 cm?3, and a deuterium concentration in a vicinity of an interface of the gate insulator film with the silicon substrate is higher than the deuterium concentration in the vicinity of the interface of the gate insulation film with the gate electrode.
    Type: Grant
    Filed: April 1, 2002
    Date of Patent: May 10, 2005
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Yuichiro Mitani, Hideki Satake
  • Publication number: 20050040481
    Abstract: An insulating film comprising: a first barrier layer;a well layer provided; and a second barrier layer is proposed. The first barrier layer consists of a material having a first bandgap and a first relative permittivity. The well layer is provided on the first barrier layer, and consists of a material having a second bandgap smaller than the first bandgap and having a second relative permittivity larger than first relative permittivity. Discrete energy levels are formed in the well layer by a quantum effect. The second barrier layer is provided on the well layer, and consists of a material having a third bandgap larger than the second bandgap and having a third relative permittivity smaller than second relative permittivity.
    Type: Application
    Filed: September 30, 2003
    Publication date: February 24, 2005
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Tatsuo Shimizu, Hideki Satake
  • Publication number: 20050017304
    Abstract: There is provided a field effect transistor including: a first insulating film formed on a semiconductor substrate, and including at least a metal oxide having a crystallinity and different in a lattice distance of a crystal on an interface from the semiconductor substrate; a convex channel region formed above the first insulating film, and different in the lattice distance from the semiconductor substrate; a source region and a drain region formed above the first insulating film on side surfaces of the channel region, respectively; a second insulating film formed right above the channel region; a gate insulating film formed on a side surface of the channel region different from the side surfaces of the channel region on which the source region and the drain regions are formed; and a gate electrode formed through the gate insulating film on at least the side surface of the channel region different from the side surfaces of the channel region on which the source region and the drain region are formed.
    Type: Application
    Filed: June 9, 2004
    Publication date: January 27, 2005
    Inventors: Daisuke Matsushita, Yukie Nishikawa, Hideki Satake, Noburu Fukushima
  • Publication number: 20040227198
    Abstract: A semiconductor device including a silicon substrate, a gate insulator film formed on the silicon substrate and including silicon, deuterium, and at least one of oxygen and nitrogen, and a gate electrode formed on the gate insulator film wherein a deuterium concentration in a vicinity of an interface of the gate insulator film with the gate electrode is at least 1×1017 cm−3, and a deuterium concentration in a vicinity of an interface of the gate insulator film with the silicon substrate is higher than the deuterium concentration in the vicinity of the interface of the gate insulation film with the gate electrode.
    Type: Application
    Filed: June 22, 2004
    Publication date: November 18, 2004
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Yuichiro Mitani, Hideki Satake
  • Publication number: 20040061181
    Abstract: A semiconductor device is proposed which includes: a semiconductor substrate of a first conductivity type; a channel region formed at a surface of the semiconductor substrate;
    Type: Application
    Filed: September 26, 2003
    Publication date: April 1, 2004
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventor: Hideki Satake