Patents by Inventor Hideki Satake

Hideki Satake has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20030209816
    Abstract: Provided is a semiconductor device including a silicon substrate, a gate insulator disposed on the silicon substrate and containing a metal oxide, a gate electrode disposed on the gate insulator, and a sidewall insulating film disposed on a side of the gate insulator and the gate electrode and containing aluminum, silicon, oxygen and nitrogen.
    Type: Application
    Filed: March 27, 2003
    Publication date: November 13, 2003
    Inventors: Takeshi Yamaguchi, Hideki Satake, Noburu Fukushima
  • Publication number: 20030183885
    Abstract: A MIS type field effect transistor including gate dielectrics having a rare-earth metal oxynitride layer with a high dielectric constant, which can maintain good interface characteristics, can be provided. A field effect transistor according to one aspect of this invention includes a gate dielectric having a substantially crystalline rare-earth metal oxynitride layer containing one or more metals selected from rare-earth metals, oxygen, and nitrogen. The rare-earth metal oxynitride layer contacts a predetermined region of a Si semiconductor substrate, and the nitrogen exists at the interface between the rare-earth metal oxynitride layer and the Si semiconductor substrate, and in the bulk of the rare-earth metal oxynitride. The transistor further includes a gate electrode formed on the gate dielectrics and source and drain regions, one being formed at one side of the gate electrode and the other being formed at the other side of the gate electrode in the Si semiconductor substrate.
    Type: Application
    Filed: March 26, 2003
    Publication date: October 2, 2003
    Applicant: Kabushiki Kaisha Toshiba
    Inventors: Yukie Nishikawa, Noburu Fukushima, Takeshi Yamaguchi, Hideki Satake
  • Publication number: 20020140043
    Abstract: A semiconductor device including a silicon substrate, a gate insulator film formed on the silicon substrate and including silicon, deuterium, and at least one of oxygen and nitrogen, and a gate electrode formed on the gate insulator film wherein a deuterium concentration in a vicinity of an interface of the gate insulator film with the gate electrode is at least 1×107 cm−3, and a deuterium concentration in a vicinity of an interface of the gate insulator film with the silicon substrate is higher than the deuterium concentration in the vicinity of the interface of the gate insulation film with the gate electrode.
    Type: Application
    Filed: April 1, 2002
    Publication date: October 3, 2002
    Applicant: KABUSHI KAISHA TOSHIBA
    Inventors: Yuichiro Mitani, Hideki Satake
  • Patent number: 6208002
    Abstract: In the manufacturing process of a field effect transistor, the main surface of the semiconductor layer is exposed to the atmosphere containing oxygen atoms and nitrogen atoms at first. Then, the gate insulating film is formed by introducing heavy hydrogen atoms therein such that the concentration of heavy hydrogen atoms in the interface of a gate insulating film and the gate electrode is higher than that of a middle portion of the gate insulating film located in the middle of the gate insulating film in the direction of the thickness of the gate insulating film. Subsequently, the gate electrode is formed on the gate insulating film. Then, source and drain regions are formed on the main surface of the semiconductor layer to sandwich the gate electrode therebetween. By virtue of the above-mentioned method, a gate insulating film having a small thickness and high electric stability can be obtained.
    Type: Grant
    Filed: January 13, 1999
    Date of Patent: March 27, 2001
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Hideki Satake, Akira Toriumi
  • Patent number: 6191463
    Abstract: A semiconductor device includes a semiconductor substrate, a first insulating film formed on the semiconductor substrate, and an electrode formed on the first insulating film. The first insulating film contains a halogen element and a combination of silicon and nitrogen or a combination of silicon, oxygen, and nitrogen. The maximum concentration of the halogen element in the first insulating film ranges from 1020 atoms/cm3 to 1021 atoms/cm3 inclusive. With this structure, the dielectric breakdown strength and the like of the insulating film increase, and the reliability of the insulating film improves.
    Type: Grant
    Filed: July 14, 1998
    Date of Patent: February 20, 2001
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Yuichiro Mitani, Hideki Satake, Akira Toriumi
  • Patent number: 6060403
    Abstract: A method of manufacturing a semiconductor device comprises the step of applying a nitridation treatment to a semiconductor substrate in the presence of a network terminal element so as to form a nitride film containing the network terminal element on the semiconductor substrate.
    Type: Grant
    Filed: September 16, 1998
    Date of Patent: May 9, 2000
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Naoki Yasuda, Masahiro Koike, Kouichi Muraoka, Hideki Satake
  • Patent number: 5969290
    Abstract: The invention provides a thermoelectric element produced by placing a powder of thermoelectric material over an electrode plate first and then an electrode plate over the power to form superposed layers, and thereafter sintering the powder with a pressure applied thereto perpendicular to the superposed layers. The electrode plates and the thermoelectric material are joined into an integral assembly before fabricating a thermoelectric module. The invention provides a thermoelectric module which is produced by arranging p-type thermoelectric elements and n-type thermoelectric elements alternately in a row at a predetermined interval, each of the elements comprising a thermoelectric material provided between and joined to a pair of opposed electrode plates, and interconnecting pairs of spaced adjacent upper electrode plates and pairs of spaced adjacent lower electrode plates alternately by brazing to electrically connect the p-type and n-type thermoelectric elements in series.
    Type: Grant
    Filed: August 1, 1997
    Date of Patent: October 19, 1999
    Assignee: Kubota Corporation
    Inventors: Shuzo Kagawa, Isao Endo, Hideki Satake, Michio Yamaguchi
  • Patent number: 5250448
    Abstract: A heterojunction bipolar transistor of this invention is a miniaturized heterojunction bipolar transistor wherein at least one of an emitter layer and a collector layer is formed of a semiconductor material having a wider band gap than a material of a base layer. A method of fabricating the transistor includes the steps of forming a first semiconductor layer of a first conductivity type on a substrate, which first semiconductor layer serves as a collector layer, etching an unnecessary portion of the first semiconductor layer to form a groove, and burying an insulating layer in the groove, forming a second semiconductor layer serving as a base layer on the first semiconductor layer and that part of the insulating layer surrounding the first semiconductor layer, and forming a third semiconductor layer of the first conductivity type, serving as an emitter layer, on the second semiconductor layer.
    Type: Grant
    Filed: January 31, 1991
    Date of Patent: October 5, 1993
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Toshihiko Hamasaki, Hideki Satake