Patents by Inventor Hideki Takeuchi

Hideki Takeuchi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11978771
    Abstract: A semiconductor gate-all-around (GAA) device may include a semiconductor substrate, source and drain regions on the semiconductor substrate, a plurality of semiconductor nanostructures extending between the source and drain regions, and a gate surrounding the plurality of semiconductor nanostructures in a gate-all-around arrangement. Furthermore, at least one superlattice may be within at least one of the nanostructures. The at least one superlattice may include a plurality of stacked groups of layers, with each group of layers including a plurality of stacked base semiconductor monolayers defining a base semiconductor portion, and at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions.
    Type: Grant
    Filed: December 21, 2022
    Date of Patent: May 7, 2024
    Assignee: ATOMERA INCORPORATED
    Inventors: Keith Doran Weeks, Nyles Wynn Cody, Marek Hytha, Robert J. Mears, Robert John Stephenson, Hideki Takeuchi
  • Patent number: 11971682
    Abstract: A cartridge includes a first unit including a photosensitive member, and a second unit including a developer bearing member and a force receiving portion, the second unit being configured to be rotatable about a first axis to move with respect to the first unit between a first position and a second position. In a state where the first unit is in a same posture as when an image forming operation is performed, the second unit is disposed at the second position by its own weight. The developer bearing member is configured to be rotatable about a second axis. When seen in the direction of the first axis, a first distance between the force receiving portion and the second axis is smaller than a second distance between the first axis and the second axis and a third distance between the first axis and the force receiving portion.
    Type: Grant
    Filed: April 10, 2023
    Date of Patent: April 30, 2024
    Assignee: Canon Kabushiki Kaisha
    Inventors: Hideki Kakuta, Toshiaki Takeuchi, Yu Akiba, Shuichi Gofuku, Tomofumi Kawamura, Yusuke Atsu, Joji Goto
  • Publication number: 20240097026
    Abstract: A semiconductor device may include a substrate and spaced apart first and second doped regions in the substrate. The first doped region may be larger than the second doped region to define an asymmetric channel therebetween. The semiconductor device may further include a superlattice extending between the first and second doped regions to constrain dopant therein. The superlattice may include a plurality of stacked groups of layers, with each group of layers comprising a plurality of stacked base semiconductor monolayers defining a base semiconductor portion, and at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions. A gate may overly the asymmetric channel.
    Type: Application
    Filed: November 21, 2023
    Publication date: March 21, 2024
    Inventors: HIDEKI TAKEUCHI, RICHARD BURTON, YUNG-HSUAN YANG
  • Patent number: 11923418
    Abstract: A semiconductor device may include a first single crystal silicon layer having a first percentage of silicon 28; a second single crystal silicon layer having a second percentage of silicon 28 higher than the first percentage of silicon 28; and a superlattice between the first and second single crystal silicon layers. The superlattice may include stacked groups of layers, with each group of layers including stacked base silicon monolayers defining a base silicon portion, and at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base silicon portions.
    Type: Grant
    Filed: April 21, 2021
    Date of Patent: March 5, 2024
    Assignee: ATOMERA INCORPORATED
    Inventors: Marek Hytha, Keith Doran Weeks, Nyles Wynn Cody, Hideki Takeuchi
  • Publication number: 20240072096
    Abstract: A method for making an image sensor device may include forming a pixel region within a semiconductor substrate comprising a first dopant having a first conductivity type, forming a first pinning layer on a surface of the substrate and including a second dopant having a second conductivity type different the first conductivity type, and forming a second pinning layer in the semiconductor substrate adjacent at least one side of the pixel region and including a superlattice and the second dopant. The superlattice may include a plurality of stacked groups of layers, with each group of layers comprising a plurality of stacked base semiconductor monolayers defining a base semiconductor portion, and at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions.
    Type: Application
    Filed: March 29, 2023
    Publication date: February 29, 2024
    Inventors: HIDEKI TAKEUCHI, YI-ANN CHEN, NYLES WYNN CODY
  • Publication number: 20240072095
    Abstract: An image sensor device may include a semiconductor substrate, a pixel region within the semiconductor substrate comprising a first dopant having a first conductivity type, a first pinning layer on a surface of the substrate and including a second dopant having a second conductivity type different the first conductivity type, and a second pinning layer in the semiconductor substrate adjacent at least one side of the pixel region and including a superlattice and the second dopant. The superlattice may include a plurality of stacked groups of layers, with each group of layers comprising a plurality of stacked base semiconductor monolayers defining a base semiconductor portion, and at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions.
    Type: Application
    Filed: March 29, 2023
    Publication date: February 29, 2024
    Inventors: HIDEKI TAKEUCHI, YI-ANN CHEN, NYLES WYNN CODY
  • Publication number: 20240063268
    Abstract: A method for making a semiconductor device may include forming a superlattice adjacent a semiconductor layer. The superlattice may include a plurality of stacked groups of layers, with each group of layers including a plurality of stacked base semiconductor monolayers defining a base semiconductor portion, and at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions. The at least one non-semiconductor monolayer in a first group of layers of the superlattice may comprise oxygen and be devoid of carbon, and the at least one non-semiconductor monolayer in a second group of layers of the superlattice may comprise carbon.
    Type: Application
    Filed: November 3, 2023
    Publication date: February 22, 2024
    Inventors: KEITH DORAN WEEKS, NYLES WYNN CODY, MAREK HYTHA, ROBERT J. MEARS, ROBERT JOHN STEPHENSON, HIDEKI TAKEUCHI
  • Patent number: 11869968
    Abstract: A semiconductor device may include a substrate and spaced apart first and second doped regions in the substrate. The first doped region may be larger than the second doped region to define an asymmetric channel therebetween. The semiconductor device may further include a superlattice extending between the first and second doped regions to constrain dopant therein. The superlattice may include a plurality of stacked groups of layers, with each group of layers comprising a plurality of stacked base semiconductor monolayers defining a base semiconductor portion, and at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions. A gate may overly the asymmetric channel.
    Type: Grant
    Filed: April 12, 2022
    Date of Patent: January 9, 2024
    Assignee: ATOMERA INCORPORATED
    Inventors: Hideki Takeuchi, Richard Burton, Yung-Hsuan Yang
  • Publication number: 20230411557
    Abstract: A semiconductor device may include at least one semiconductor layer including a superlattice therein. The superlattice may include a plurality of stacked groups of layers, with each group of layers including stacked base semiconductor monolayers defining a base semiconductor portion, and at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions. The semiconductor device may further include quantum dots spaced apart in the at least one semiconductor layer above the superlattice and including a different semiconductor material than the semiconductor layer.
    Type: Application
    Filed: June 21, 2023
    Publication date: December 21, 2023
    Inventors: MAREK HYTHA, NYLES WYNN CODY, ROBERT J. MEARS, HIDEKI TAKEUCHI, KEITH DORAN WEEKS
  • Publication number: 20230411491
    Abstract: A method for making a semiconductor device may include forming at least one semiconductor layer including a superlattice therein. The superlattice may include a plurality of stacked groups of layers, with each group of layers including stacked base semiconductor monolayers defining a base semiconductor portion, and at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions. The method may further include forming quantum dots spaced apart in the at least one semiconductor layer above the superlattice and including a different semiconductor material than the semiconductor layer.
    Type: Application
    Filed: June 21, 2023
    Publication date: December 21, 2023
    Inventors: MAREK HYTHA, NYLES WYNN CODY, ROBERT J. MEARS, HIDEKI TAKEUCHI, KEITH DORAN WEEKS
  • Patent number: 11848356
    Abstract: A method for making a semiconductor device may include forming a superlattice adjacent a semiconductor layer. The superlattice may include a plurality of stacked groups of layers, with each group of layers including a plurality of stacked base semiconductor monolayers defining a base semiconductor portion, and at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions. The at least one non-semiconductor monolayer in a first group of layers of the superlattice may comprise oxygen and be devoid of carbon, and the at least one non-semiconductor monolayer in a second group of layers of the superlattice may comprise carbon.
    Type: Grant
    Filed: June 30, 2021
    Date of Patent: December 19, 2023
    Assignee: ATOMERA INCORPORATED
    Inventors: Keith Doran Weeks, Nyles Wynn Cody, Marek Hytha, Robert J. Mears, Robert John Stephenson, Hideki Takeuchi
  • Publication number: 20230395374
    Abstract: A method for making a semiconductor device may include forming a first single crystal silicon layer having a first percentage of silicon 28, and forming a superlattice above the first single crystal silicon layer. The superlattice may include a plurality of stacked groups of layers, with each group of layers comprising a plurality of stacked base silicon monolayers defining a base silicon portion, and at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base silicon portions. The method may further include forming a second single crystal silicon layer above the superlattice having a second percentage of silicon 28 higher than the first percentage of silicon 28.
    Type: Application
    Filed: August 23, 2023
    Publication date: December 7, 2023
    Inventors: MAREK HYTHA, KEITH DORAN WEEKS, NYLES WYNN CODY, HIDEKI TAKEUCHI
  • Patent number: 11837634
    Abstract: A semiconductor device may include a semiconductor layer and a superlattice adjacent the semiconductor layer. The superlattice may include a plurality of stacked groups of layers, with each group of layers comprising a plurality of stacked base semiconductor monolayers defining a base semiconductor portion, and at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions. The at least one non-semiconductor monolayer in a first group of layers of the superlattice may comprise oxygen and be devoid of carbon, and the at least one non-semiconductor monolayer in a second group of layers of the superlattice may comprise carbon.
    Type: Grant
    Filed: June 30, 2021
    Date of Patent: December 5, 2023
    Assignee: ATOMERA INCORPORATED
    Inventors: Keith Doran Weeks, Nyles Wynn Cody, Marek Hytha, Robert J. Mears, Robert John Stephenson, Hideki Takeuchi
  • Patent number: 11810784
    Abstract: A method for making a semiconductor device may include forming a first single crystal silicon layer having a first percentage of silicon 28, and forming a superlattice above the first single crystal silicon layer. The superlattice may include a plurality of stacked groups of layers, with each group of layers comprising a plurality of stacked base silicon monolayers defining a base silicon portion, and at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base silicon portions. The method may further include forming a second single crystal silicon layer above the superlattice having a second percentage of silicon 28 higher than the first percentage of silicon 28.
    Type: Grant
    Filed: April 21, 2021
    Date of Patent: November 7, 2023
    Assignee: ATOMERA INCORPORATED
    Inventors: Marek Hytha, Keith Doran Weeks, Nyles Wynn Cody, Hideki Takeuchi
  • Publication number: 20230352299
    Abstract: A method for making a radio frequency (RF) semiconductor device may include forming an RF ground plane layer on a semiconductor-on-insulator substrate and including a conductive superlattice. The conductive superlattice may include stacked groups of layers, with each group of layers including stacked doped base semiconductor monolayers defining a doped base semiconductor portion, and at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent doped base semiconductor portions. The method may further include forming a body above the RF ground plane layer, forming spaced apart source and drain regions adjacent the body and defining a channel region in the body, and forming a gate overlying the channel region.
    Type: Application
    Filed: June 22, 2023
    Publication date: November 2, 2023
    Inventors: HIDEKI TAKEUCHI, ROBERT J. MEARS
  • Publication number: 20230286998
    Abstract: An object of the present invention is to provide a compound which has high storage stability and is suitable for use as a drug substance. The present invention relates to a succinate salt of 1-{[(4aR,6R,8aR)-2-amino-3-cyano-8-methyl-4,4a,5,6,7,8,8a,9-octahydrothieno[3,2-g]quinolin-6-yl]carbonyl}-3-[2-(dimethylamino)ethyl]-1-propylurea, which is suitable as a drug substance having excellent storage stability and crystallinity and is useful for the treatment or prevention of Parkinson's disease, restless legs syndrome, hyperprolactinemia or the like.
    Type: Application
    Filed: July 5, 2021
    Publication date: September 14, 2023
    Applicant: KISSEI PHARMACEUTICAL CO., LTD.
    Inventors: Hideki TAKEUCHI, Kazumichi JO
  • Patent number: 11742202
    Abstract: A method for making a radio frequency (RF) semiconductor device may include forming an RF ground plane layer on a semiconductor-on-insulator substrate and including a conductive superlattice. The conductive superlattice may include stacked groups of layers, with each group of layers including stacked doped base semiconductor monolayers defining a doped base semiconductor portion, and at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent doped base semiconductor portions. The method may further include forming a body above the RF ground plane layer, forming spaced apart source and drain regions adjacent the body and defining a channel region in the body, and forming a gate overlying the channel region.
    Type: Grant
    Filed: March 3, 2022
    Date of Patent: August 29, 2023
    Assignee: ATOMERA INCORPORATED
    Inventors: Hideki Takeuchi, Robert J. Mears
  • Publication number: 20230183241
    Abstract: As a drug substance, a crystal having good physical properties is preferable. However, the crystal form that is most excellent as a drug substance may vary with the compound. In general, it is difficult to predict a crystal form of a drug substance having good physical properties, and it is required to variously examine each compound. Therefore, an object of the present invention is to provide a crystal having good physical properties as a drug substance for a novel compound. The present invention relates to a crystal of the compound represented by the following formula (I) useful for the treatment of an inflammatory bowel disease.
    Type: Application
    Filed: March 10, 2021
    Publication date: June 15, 2023
    Applicant: Kissei Pharmaceutical Co., Ltd.
    Inventors: Yoshiro Kijima, Hideki Takeuchi, Yasushi Takigawa, Yusuke Kawabe
  • Publication number: 20230167108
    Abstract: As a drug substance, a crystal having good physical properties is preferable. However, the crystal form that is most excellent as a drug substance may vary with the compound. In general, it is difficult to predict a crystal form of a drug substance having good physical properties, and it is required to variously examine each compound. Therefore, an object of the present invention is to provide a crystal having good physical properties as a drug substance for a novel compound or a salt thereof. The present invention relates to a crystal of the compound represented by the following formula (I) or a salt thereof useful for the treatment of an inflammatory bowel disease.
    Type: Application
    Filed: March 10, 2021
    Publication date: June 1, 2023
    Applicant: Kissei Pharmaceutical Co., Ltd.
    Inventors: Hideki Takeuchi, Yoshiro Kijima, Akihiro Moriyama
  • Publication number: 20230121774
    Abstract: A semiconductor gate-all-around (GAA) device may include a semiconductor substrate, source and drain regions on the semiconductor substrate, a plurality of semiconductor nanostructures extending between the source and drain regions, and a gate surrounding the plurality of semiconductor nanostructures in a gate-all-around arrangement. Furthermore, at least one superlattice may be within at least one of the nanostructures. The at least one superlattice may include a plurality of stacked groups of layers, with each group of layers including a plurality of stacked base semiconductor monolayers defining a base semiconductor portion, and at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions.
    Type: Application
    Filed: December 21, 2022
    Publication date: April 20, 2023
    Inventors: KEITH DORAN WEEKS, NYLES WYNN CODY, MAREK HYTHA, ROBERT J. MEARS, ROBERT JOHN STEPHENSON, HIDEKI TAKEUCHI