Abstract: A method for making a semiconductor device may include forming spaced apart shallow trench isolation (STI) regions in a semiconductor layer, etching first portions of the semiconductor layer between adjacent ones of the STI regions to an etch depth, and performing a well implant in the first portions of the semiconductor layer. The method may further include forming respective superlattices on the first portions of the semiconductor layer between the adjacent ones of STI regions and with a height not greater than the etch depth. The method may also include forming respective spaced apart source and drain regions associated with each superlattice, and forming a respective gate above each superlattice.

Abstract: A method for making a semiconductor device may include implanting non-semiconductor atoms into a localized region of a semiconductor layer, and forming a superlattice on the semiconductor layer over the localized region. The superlattice may include a stacked groups of layers, with each group of layers including stacked base semiconductor monolayers defining a base semiconductor portion, and at least one monolayer of the non-semiconductor atoms constrained within a crystal lattice of adjacent base semiconductor portions. The method may also include performing a thermal treatment to cause non-semiconductor atoms from the superlattice to be displaced, and to cause non-semiconductor atoms from the localized region to migrate into the superlattice and replace at least some of the displaced non-semiconductor atoms.

Abstract: A semiconductor device may include a substrate and spaced apart first and second doped regions in the substrate. The first doped region may be larger than the second doped region to define an asymmetric channel therebetween. The semiconductor device may further include a superlattice extending between the first and second doped regions to constrain dopant therein. The superlattice may include a plurality of stacked groups of layers, with each group of layers comprising a plurality of stacked base semiconductor monolayers defining a base semiconductor portion, and at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions. A gate may overly the asymmetric channel.

Abstract: A memory device may include an array of memory cells on a semiconductor substrate. Each memory cell may include a first well in the semiconductor substrate having a first conductivity type, a second well adjacent the first well and having a second conductivity type and defining a depletion layer with the first well, and nanocrystals within the depletion region, with each nanocrystal comprising a semiconductor material and carbon. The memory device may further include spaced apart source and drain regions adjacent the second well and defining a channel therebetween, and a gate overlying the channel.

Abstract: A memory device may include an array of memory cells on a semiconductor substrate. Each memory cell may include a first well on the semiconductor substrate having a first conductivity type, a second well adjacent the first well and having a second conductivity type and defining a depletion layer with the first well, and a superlattice within the depletion layer. The superlattice may include stacked groups of layers, with each group of layers comprising stacked base semiconductor monolayers defining a base semiconductor portion, and a non-semiconductor monolayer(s) constrained within a crystal lattice of adjacent base semiconductor portions. Trap source atoms may also be within the stacked groups of layers. Each memory cell may further include spaced apart source and drain regions adjacent the second well and defining a channel therebetween, and a gate overlying the channel.

Abstract: A method for making a memory device may include forming an array of memory cells on a semiconductor substrate. Each memory cell may include a first well on the semiconductor substrate having a first conductivity type, a second well adjacent the first well and having a second conductivity type and defining a depletion layer with the first well, and a superlattice within the depletion layer. The superlattice may include stacked groups of layers, with each group of layers comprising stacked base semiconductor monolayers defining a base semiconductor portion, and a non-semiconductor monolayer(s) constrained within a crystal lattice of adjacent base semiconductor portions, and trap source atoms within the stacked groups of layers. Each memory call may also include spaced apart source and drain regions adjacent the second well and defining a channel therebetween, and a gate overlying the channel.

Abstract: A method for making a memory device may include forming an array of memory cells on a semiconductor substrate. Each memory cell may include a first well in the semiconductor substrate having a first conductivity type, a second well adjacent the first well and having a second conductivity type and defining a depletion layer with the first well, and nanocrystals within the depletion region, with each nanocrystal comprising a semiconductor material and carbon. The memory device may further include spaced apart source and drain regions adjacent the second well and defining a channel therebetween, and a gate overlying the channel.

Abstract: A method for making a semiconductor gate-all-around (GAA) device may include forming source and drain regions on a semiconductor substrate, forming a plurality of semiconductor nanostructures extending between the source and drain regions, and forming a gate surrounding the plurality of semiconductor nanostructures in a gate-all-around arrangement. Furthermore, the method may include forming at least one superlattice may be within at least one of the nanostructures. The at least one superlattice may include a plurality of stacked groups of layers, with each group of layers including a plurality of stacked base semiconductor monolayers defining a base semiconductor portion, and at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions.

Abstract: A semiconductor device may include a substrate and spaced apart first and second doped regions in the substrate. The first doped region may be larger than the second doped region to define an asymmetric channel therebetween. The semiconductor device may further include a superlattice extending between the first and second doped regions to constrain dopant therein. The superlattice may include a plurality of stacked groups of layers, with each group of layers comprising a plurality of stacked base semiconductor monolayers defining a base semiconductor portion, and at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions. A gate may overly the asymmetric channel.

Abstract: A method for making a semiconductor device may include forming a superlattice gettering layer on a substrate. The superlattice may include a plurality of stacked groups of layers, with each group of layers comprising a plurality of stacked base semiconductor monolayers defining a base semiconductor portion, and at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions. The method may also include forming a memory device above the superlattice gettering layer including a metal induced crystallization (MIC) channel adjacent the semiconductor substrate, and a gate associated with the MIC channel. The superlattice gettering layer may further include gettered metal particles from the MIC channel.

Abstract: A semiconductor device may include a semiconductor substrate and a memory device on the semiconductor substrate including a metal induced crystallization (MIC) channel adjacent the semiconductor substrate, and a gate associated with the MIC channel. The semiconductor device may further include a superlattice gettering layer between the substrate and the MIC channel. The superlattice gettering layer may include a plurality of stacked groups of layers, with each group of layers comprising a plurality of stacked base semiconductor monolayers defining a base semiconductor portion, and at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions. The superlattice gettering layer may further include gettered metal particles from the MIC channel.

Abstract: A method for making a semiconductor device may include forming a superlattice adjacent a semiconductor layer. The superlattice may include a plurality of stacked groups of layers, with each group of layers including a plurality of stacked base semiconductor monolayers defining a base semiconductor portion, and at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions. The at least one non-semiconductor monolayer in a first group of layers of the superlattice may comprise oxygen and be devoid of carbon, and the at least one non-semiconductor monolayer in a second group of layers of the superlattice may comprise carbon.

Abstract: A method for making a semiconductor gate-all-around (GAA) device may include forming source and drain regions on a semiconductor substrate, forming a plurality of semiconductor nanostructures extending between the source and drain regions, and forming a gate surrounding the plurality of semiconductor nanostructures in a gate-all-around arrangement. Furthermore, the method may include forming at least one superlattice may be within at least one of the nanostructures. The at least one superlattice may include a plurality of stacked groups of layers, with each group of layers including a plurality of stacked base semiconductor monolayers defining a base semiconductor portion, and at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions.

Abstract: A semiconductor device may include a semiconductor substrate, buried spaced-apart insulator regions in the substrate, and a monocrystalline semiconductor layer on the semiconductor substrate defining respective localized semiconductor on insulator (SOI) regions above the buried insulator regions, and respective localized bulk semiconductor regions laterally between adjacent SOI regions. The semiconductor device may also include a superlattice in the monocrystalline semiconductor layer. The superlattice may include stacked groups of layers, with each group of layers including stacked base semiconductor monolayers defining a base semiconductor portion, and at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions.

Abstract: A method for making a semiconductor device may include forming buried spaced-apart insulator regions in a semiconductor substrate, and forming a monocrystalline semiconductor layer on the semiconductor substrate defining respective localized semiconductor on insulator (SOI) regions above the buried insulator regions, and respective localized bulk semiconductor regions laterally between adjacent SOI regions. The method may also include forming a superlattice in the monocrystalline semiconductor layer. The superlattice may include stacked groups of layers, with each group of layers including stacked base semiconductor monolayers defining a base semiconductor portion, and at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions.

Abstract: A method for making a semiconductor device may include forming a superlattice adjacent a semiconductor layer. The superlattice may include a plurality of stacked groups of layers, with each group of layers including a plurality of stacked base semiconductor monolayers defining a base semiconductor portion, and at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions. The at least one non-semiconductor monolayer in a first group of layers of the superlattice may comprise oxygen and be devoid of carbon, and the at least one non-semiconductor monolayer in a second group of layers of the superlattice may comprise carbon.

Abstract: A method for making a semiconductor device may include forming a first single crystal silicon layer having a first percentage of silicon 28, and forming a superlattice above the first single crystal silicon layer. The superlattice may include a plurality of stacked groups of layers, with each group of layers comprising a plurality of stacked base silicon monolayers defining a base silicon portion, and at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base silicon portions. The method may further include forming a second single crystal silicon layer above the superlattice having a second percentage of silicon 28 higher than the first percentage of silicon 28.

Abstract: A radio frequency (RF) semiconductor device may include a semiconductor-on-insulator substrate, and an RF ground plane layer on the semiconductor-on-insulator substrate including a conductive superlattice. The conductive superlattice may include stacked groups of layers, with each group of layers comprising stacked doped base semiconductor monolayers defining a doped base semiconductor portion, and at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent doped base semiconductor portions. The RF semiconductor device may further include a body above the RF ground plane layer, spaced apart source and drain regions adjacent the body and defining a channel region in the body, and a gate overlying the channel region.

Abstract: A method for making a radio frequency (RF) semiconductor device may include forming an RF ground plane layer on a semiconductor-on-insulator substrate and including a conductive superlattice. The conductive superlattice may include stacked groups of layers, with each group of layers including stacked doped base semiconductor monolayers defining a doped base semiconductor portion, and at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent doped base semiconductor portions. The method may further include forming a body above the RF ground plane layer, forming spaced apart source and drain regions adjacent the body and defining a channel region in the body, and forming a gate overlying the channel region.

Abstract: A semiconductor processing method may include forming a superlattice layer on a donor semiconductor wafer, the superlattice including a plurality of stacked groups of layers, each group of layers comprising a plurality of stacked base semiconductor monolayers defining a base semiconductor portion, and at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions. The method may further include performing ion implantation on the donor semiconductor wafer to create a separation layer below the superlattice layer, forming an oxide layer on a base semiconductor wafer, performing ion beam treatment on the oxide layer, bonding the donor semiconductor wafer to the base semiconductor wafer so that the superlattice layer is adjacent the oxide layer, removing portions of the donor wafer at the separation layer from the donor wafer to define an active semiconductor layer above the superlattice layer, and forming an electronic device(s) in the active layer.