Patents by Inventor Hideki Taniguchi

Hideki Taniguchi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 6310493
    Abstract: In a semiconductor integrated circuit, an input-output circuit includes a flip-flop circuit (a front stage of an output circuit) between an input circuit unit and a tri-state output circuit unit (a final stage of an output circuit). This input-output circuit converts the level of the signal supplied from an internal circuit, which is operated by a first power source system, which provides a first supply potential and a grounding potential, of an LSI. After elapse of a certain time delay, the input-output circuit outputs a level converted signal to a device, which is operated by a second power source system, providing a second supply potential and a grounding potential, outside of the LSI.
    Type: Grant
    Filed: June 23, 2000
    Date of Patent: October 30, 2001
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventor: Hideki Taniguchi
  • Patent number: 6278294
    Abstract: To prevent a through current from flowing through a pair of MOS transistors of a final stage of a push-pull buffer circuit, a reset circuit is provided which receives signals individually from two inverter gate groups of a control system and an output system disposed at the stage preceding the push-pull buffer circuit, delays the input signals, and makes a logical decision on them. Even when an input/output circuit formed by two power supply systems becomes unstable at the time of power ON-OFF operation and the signal output from a signal level converter circuit yields logic that causes a through current flow into the final stage, the reset circuit forcedly cancels this logic by feedback.
    Type: Grant
    Filed: October 15, 1999
    Date of Patent: August 21, 2001
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventor: Hideki Taniguchi
  • Patent number: 6130484
    Abstract: A semiconductor device includes a buffer region having buffers and disposed along a side of a semiconductor chip; a pad region having pads corresponding to the buffers and disposed outside the buffer region on the semiconductor chip; signal lines connecting the buffers to corresponding pads; and power supply lines and ground lines connected to extra pads, either of the power supply lines or the ground lines being partially superimposed on part of and separated from the signal lines by insulating layers.
    Type: Grant
    Filed: December 12, 1997
    Date of Patent: October 10, 2000
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventors: Hideo Kameda, Naoto Ueda, Yoichi Goi, Hideki Taniguchi
  • Patent number: 6107832
    Abstract: An input/output circuit in which, one of the two output signals from a signal level converting circuit is inputted into one input terminal of a NAND gate and into one input terminal of a NOR gate, while the other signal is inputted into the other input terminal of the NOR gate and also to the other input terminal of the NAND gate through an inverter. An output signal from the NAND gate and NOR gate is inputted into the gate of a PMOS transistor and into a gate of a NMOS transistor, which makes it possible to prevent the PMOS transistor and NMOS transistor from concurrently being ON and also prevents a through current from flowing therethrough.
    Type: Grant
    Filed: May 28, 1999
    Date of Patent: August 22, 2000
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventor: Hideki Taniguchi
  • Patent number: 6094067
    Abstract: An output buffer circuit is provided which comprises a level conversion circuit having a first conversion circuit for converting a control signal and an output signal to "H" and "L" signals in a first source system and a second conversion circuit for converting these into "H" and "L" signals in a second source system, a tristate control type input/output control circuit for computing the "H" and "L" signals outputted from the second conversion circuit in the second source system, and a push-pull circuit having MOS transistors Q13a and Q14, which is activated in the second source system in response to the "H" and "L" signals so as to select a tristate and output it as an input/output signal.
    Type: Grant
    Filed: September 16, 1997
    Date of Patent: July 25, 2000
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventor: Hideki Taniguchi
  • Patent number: 6066958
    Abstract: There are provided an output buffer circuit and an input/output buffer circuit each including pre-driver circuit and main driver circuit divided to a plurality of stages and a delay circuit and enabling operations of the main driver circuit successively with a delay circuit in the pre-driver circuit.
    Type: Grant
    Filed: November 18, 1998
    Date of Patent: May 23, 2000
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventors: Hideki Taniguchi, Yoichi Goi
  • Patent number: 6054620
    Abstract: The present invention provides a process for producing a tertiary aliphatic amine having high quality having little non-amines such as esters and alcohols, which is less colored, and which can be converted into a derivative without turbidity.That is, the present invention provides the process which comprises the steps of adding at least one alkali substance of potassium hydroxide and sodium hydroxide or an aqueous solution thereof to the crude tertiary amine product mixture and distilling the mixture to obtain the tertiary amine having a high quality.In addition, the tertiary amine has the formula: R.sub.1 R.sub.2 N--R.sub.3, wherein R.sub.1 and R.sub.2 being a saturated or unsaturated hydrocarbon having 6 to 28 carbon atoms, R.sub.3 being a saturated or unsaturated hydrocarbon having 1 to 5 carbon atoms.
    Type: Grant
    Filed: September 28, 1998
    Date of Patent: April 25, 2000
    Assignee: Kao Corporation
    Inventors: Hideki Taniguchi, Yasuyuki Mimura, Hiroshi Abe
  • Patent number: 6025108
    Abstract: The developing process of this invention comprises supplying a charged toner to a development roller disposed against a photosensitive drum, forming a thin layer of the charged toner on the development roller by a blade press-contacted with the development roller, and contacting this thin layer of the charged toner on the surface of the photosensitive drum on which an electrostatic latent image is formed. The process further comprises using a non-magnetic toner which has a circularity degree of more than 0.94 and which has a falling amount of at least 10 g/5 minutes as measured by a tester for measuring the amount of falling. By using such a toner, it is possible to prevent the collection of the toner on the bottom of a development housing which includes various members for practicing the above process, and it is also possible to prevent the rising of a driving torque of the rollers.
    Type: Grant
    Filed: October 22, 1998
    Date of Patent: February 15, 2000
    Assignee: Mita Industrial Co., Ltd.
    Inventors: Atsushi Hujii, Nariaki Tanaka, Hideki Taniguchi
  • Patent number: 5973509
    Abstract: An output buffer circuit for controlling operation of an input and output terminal utilizing a pair of MOS Transistors respectively formed in first and second wells in a substrate. The input and output terminal is connected commonly to the source of the first MOS transistor, to the drain of the second MOS transistor and to the well of the first MOS transistor in order to hold the well at the same potential as the input and output terminal. Also included is a first potential point applying a first potential to the drain of the first MOS transistor and a second potential apply commonly to the source and the well electrode of the second MOS transistor. The resulting structure controls the operating state of the input and output terminal in a manner which allows for an enhanced output potential.
    Type: Grant
    Filed: March 27, 1998
    Date of Patent: October 26, 1999
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventors: Hideki Taniguchi, Katsushi Asahina
  • Patent number: 5828260
    Abstract: A detecting penetration current causing logic part (12a) gives, when the logic is H level at both nodes (N15, N24), the logical product thereof H to a condition adding part (12b) as an activated detection signal. In the condition adding part (12b), it is confirmed that the activation of the detection signal is longer than a specified time, by a delay circuit (G21) and NAND gate (G22). Consequently, logic H is given to a forced logic presenting part (12c). In the forced logic presenting part (12c), NMOS transistors (Q13, Q14) are turned on, and logic L is given by force to both nodes (N15, N24) to get out of a state where a current would flow.
    Type: Grant
    Filed: May 16, 1996
    Date of Patent: October 27, 1998
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventors: Hideki Taniguchi, Katsushi Asahina
  • Patent number: 5703264
    Abstract: The process for producing an aliphatic nitrile comprising reacting an aliphatic alcohol having 6 to 40 carbon atoms with ammonia (a) in the presence of a copper/transition metal element in the fourth period other than Cr/platinum group element in the eighth group catalyst, (b) under a reaction system pressure in the range of from atmospheric pressure to 100 atm, (c) at a reaction system temperature in the range of from 100.degree. to 250.degree. C., (d) while introducing at least one gas selected from the group consisting of inert gases and hydrogen gas into the reaction system, (e) removing water formed by the reaction out of the reaction system, and (f) controlling the amount of the ammonia contained in the gas (exclusive of the water formed by the reaction) discharged out of the reaction system to 5 to 50% by volume based on the volume of the gas discharged (exclusive of the water formed by the reaction) makes it possible to produce various kinds of aliphatic nitriles.
    Type: Grant
    Filed: June 24, 1996
    Date of Patent: December 30, 1997
    Assignee: Kao Corporation
    Inventors: Wataru Yoshida, Tetsuaki Fukushima, Hideki Taniguchi, Hiroshi Abe
  • Patent number: 5696294
    Abstract: N,N-Dimethyl-N-alkylamine or -alkenylamine is prepared by reacting a higher alcohol and dimethylamine by passing hydrogen gas and dimethylamine into a reactor containing a catalyst for the reaction at a pressure of atmospheric pressure to 100 atm. at 150.degree. C. to 250.degree. C. and removing water produced in the reaction as a component of the mixed hydrogen and unreacted dimethylamine gas which is discharged from the reactor, wherein at the point in the reaction at which from 90 to 99% of the higher alcohol has reacted with dimethylamine, one of the following procedures is followed: i) the introduction of only dimethylamine gas into the reactor is stopped, and the reaction is allowed to continue at a temperature 20.degree. to 150.degree. C. lower than the reaction temperature recited above; ii) the introduction of only dimethylamine gas into the reactor is stopped while the temperature is decreased to a level of 20.degree. to 150.degree. C.
    Type: Grant
    Filed: September 19, 1996
    Date of Patent: December 9, 1997
    Assignee: Kao Corporation
    Inventors: Hiroshi Abe, Hideki Taniguchi, Tetsuaki Fukushima
  • Patent number: 5552618
    Abstract: A master-slice semiconductor integrated circuit device includes a substrate for an input/output circuit section, which is segmented into a plurality of segments during a master processing step. In a slice processing step, slice cells are formed, using different substrate segments. Input/output circuits are formed by respective slice cells so that desired different supply voltages can be applied to input/output circuits on different substrate segments.
    Type: Grant
    Filed: October 19, 1994
    Date of Patent: September 3, 1996
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventors: Hideki Taniguchi, Ichiro Tomioka, Kunihiko Sanada, Masatomi Okabe
  • Patent number: 5488168
    Abstract: A tertiary amino alcohol, being useful as an emulsifier, is defined by the formula (1) or (2): ##STR1## where R is a C.sub.2 to C.sub.24 straight-chain or branched alkylene group, an alicyclic alkylene group, an aralkylene group or --CH.sub.2 CH.sub.2 O).sub.p (CH.sub.2 CH.sub.2).sub.q (where p is 0 or a positive integer and q is a positive integer), R' is a C.sub.1 to C.sub.24 straight-chain or branched alkyl group or an aralkyl group and n is a positive integer of 2 to 50.
    Type: Grant
    Filed: April 14, 1993
    Date of Patent: January 30, 1996
    Assignee: Kao Corporation
    Inventors: Kohshiro Sotoya, Hiroshi Abe, Jun Aikawa, Hideki Taniguchi, Uichiro Nishimoto
  • Patent number: 5434436
    Abstract: A plurality of different power source potentials are optionally selected in a semiconductor integrated circuit. First and second semiconductor segments (3) and (4) are both in the form of a number of rows which are separated from each other by spacings (14). Power source wires (6) and (7) for supplying potentials (V1) and (V2) are disposed above the second semiconductor regions (4). Cells are formed in different wells, and therefore, it is possible that different cells receive different power source potentials. Contacts (61) or (71) are made to the second semiconductor segments (4) so that the second semiconductor segments (4) are connected to the power source wire (6) or (7). Selection of and connection to one of the wires are attained in a slicing process.
    Type: Grant
    Filed: June 25, 1993
    Date of Patent: July 18, 1995
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventors: Hideki Taniguchi, Masahiro Suzuki
  • Patent number: 5404035
    Abstract: A master-slice semiconductor integrated circuit device includes a substrate for an input/output circuit section, which is segmented into a plurality of segments during a master processing step. In a slice processing step, slice cells are formed, using different substrate segments. Input/output circuits are formed by respective slice cells so that desired different supply voltages can be applied to input/output circuits on different substrate segments.
    Type: Grant
    Filed: June 10, 1993
    Date of Patent: April 4, 1995
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventors: Hideki Taniguchi, Ichiro Tomioka, Kunihiko Sanada, Masatomi Okabe
  • Patent number: 5296631
    Abstract: A process for producing an N-alkyl-N-methylamine or an N-alkenyl-N-methylamine in a high yield from a higher alcohol and methylamine comprising the step of reacting a higher alcohol with methylamine in the presence of a catalyst comprising copper and a fourth period transition metal of the Periodic Table, except for chromium, or a catalyst comprising copper, a fourth period transition metal of the Periodic Table, except for chromium, and an element of the platinum group VIII of the Periodic Table, at a pressure ranging from atmospheric pressure to 100 atm. G., at a reaction temperature ranging from 100.degree. to 250.degree. C., with hydrogen gas being introduced into the reaction system while water produced in the reaction is removed from the reaction system and the amount of methylamine in the gaseous mixture which contains no matter formed through the reaction and is exhausted from the reaction system is regulated from 5 to 50% by volume.
    Type: Grant
    Filed: April 21, 1992
    Date of Patent: March 22, 1994
    Assignee: Kao Corporation
    Inventors: Hiroshi Abe, Hideki Taniguchi, Yoshifumi Nishimoto, Kohshiro Sotoya
  • Patent number: 4792622
    Abstract: A secondary amine is effectively prepared by reacting an alcohol or an aldehyde with a primary amine in the presence of a catalyst of copper, nickel and a metal element belonging to the platinum group VIII at a pressure of the atmospheric pressure to 5 kg/cm.sup.2 G at a temperature of 150.degree. to 250.degree. C., while water produced in the reaction is being removed out, and separating the resulting secondary amine from the product mixture.
    Type: Grant
    Filed: November 21, 1986
    Date of Patent: December 20, 1988
    Assignee: Kao Corporation
    Inventors: Yukinaga Yokota, Yuzi Sawamoto, Hideki Taniguchi, Kazuhiko Okabe
  • Patent number: 4625063
    Abstract: A tertiary amine of a high purity is prepared from an alcohol or an aldehyde and a primary or second amine at a low temperature, using a catalyst of copper, nickel and an element belonging to the VIII platinum group such as platinum, palladium, ruthenium and rhodium, while removing out water formed by the reaction.
    Type: Grant
    Filed: June 6, 1985
    Date of Patent: November 25, 1986
    Assignee: Kao Corporation
    Inventors: Yukinaga Yokota, Yuji Sawamoto, Hideki Taniguchi, Kazuhiko Okabe