Patents by Inventor Hideki Uochi

Hideki Uochi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240087487
    Abstract: A semiconductor device having favorable display quality is provided. The semiconductor device is provided with a display portion, a line-of-sight sensor portion, a control portion, and an arithmetic portion. The line-of-sight sensor portion has a function of obtaining first information showing a direction of a user's line of sight. The arithmetic portion has a function of determining a first region including a gaze point of the user on the display portion with use of the first information and a function of increasing a definition of an image displayed on the first region. Light emitted from the display portion may be used to obtain the first information showing the direction of the line of sight.
    Type: Application
    Filed: January 18, 2022
    Publication date: March 14, 2024
    Inventors: Shunpei YAMAZAKI, Yosuke TSUKAMOTO, Koji KUSUNOKI, Hisao IKEDA, Akio ENDO, Yoshiaki OIKAWA, Hideki UOCHI
  • Patent number: 11922987
    Abstract: A novel storage device is provided. The storage device includes a first wiring, a second wiring, and a first memory cell. The first memory cell includes a first transistor and a first magnetic tunnel junction device. One of a source or a drain of the first transistor is electrically connected to a first wiring. The other of the source or the drain of the first transistor is electrically connected to one terminal of the first magnetic tunnel junction device. Another terminal of the first magnetic tunnel junction device is electrically connected to the second wiring. The first transistor includes an oxide semiconductor in its channel formation region.
    Type: Grant
    Filed: December 14, 2022
    Date of Patent: March 5, 2024
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Yoshiaki Oikawa, Atsushi Miyaguchi, Hideki Uochi
  • Patent number: 11922999
    Abstract: A novel memory device is provided. The memory device includes a plurality of memory cells, and one memory cell includes a first transistor and a second transistor. One of a source and a drain of the first transistor is electrically connected to a gate of the second transistor through a node SN. Data written through the first transistor is retained at the node SN. When an OS transistor is used as the first transistor, formation of a storage capacitor is not needed. A region with a low dielectric constant is provided outside the memory cell, whereby noise from the outside is reduced and stable operation is achieved.
    Type: Grant
    Filed: September 8, 2022
    Date of Patent: March 5, 2024
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Takahiko Ishizu, Toshihiko Saito, Hideki Uochi, Shunpei Yamazaki
  • Patent number: 11899329
    Abstract: It is an object of the present invention to apply a sufficient electrical field to a liquid crystal material in a horizontal electrical field liquid crystal display device typified by an FFS type. In a horizontal electrical field liquid crystal display, an electrical field is applied to a liquid crystal material right above a common electrode and a pixel electrode using plural pairs of electrodes rather than one pair of electrodes. One pair of electrodes includes a comb-shaped common electrode and a comb-shaped pixel electrode. Another pair of electrodes includes a common electrode provided in a pixel portion and the comb-shaped pixel electrode.
    Type: Grant
    Filed: February 22, 2023
    Date of Patent: February 13, 2024
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Hajime Kimura, Hideki Uochi
  • Patent number: 11796871
    Abstract: A highly reliable display device is provided. In a flexible display device including at least a first display region and a second display region, at least a portion of a wiring provided in the first display region or the second display region has a meandering shape or a chain-like shape. Since the wiring has a meandering shape or a chain-like shape, a short-circuit, a disconnection, or the like of the wiring due to curving or bending of the display device does not occur easily. The wiring having a meandering shape or a chain-like shape can prevent defective operation, lowered reliability, or the like of the display device.
    Type: Grant
    Filed: July 28, 2021
    Date of Patent: October 24, 2023
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Daisuke Kubota, Hideki Uochi
  • Publication number: 20230326503
    Abstract: A semiconductor device that has reduced power consumption and is capable of non-destructive reading is provided. The semiconductor device includes a first circuit including a first transistor and a first FTJ element, and a second circuit including a second transistor and a second FTJ element. A first terminal of the first transistor is electrically connected to an output terminal of the first FTJ element, and a first terminal of the second transistor is electrically connected to an input terminal of the second FTJ element. A second terminal of the first transistor and a second terminal of the second transistor are electrically connected to a read circuit. In a data writing method, a voltage is applied between the input terminal and the output terminal of each of the first FTJ element and the second FTJ element to polarize the first FTJ element and the second FTJ element.
    Type: Application
    Filed: September 13, 2021
    Publication date: October 12, 2023
    Inventors: Shunpei YAMAZAKI, Hajime KIMURA, Hideki UOCHI, Atsushi MIYAGUCHI, Tatsunori INOUE
  • Publication number: 20230290789
    Abstract: A protective circuit includes a non-linear element which includes a gate electrode, a gate insulating layer covering the gate electrode, a first oxide semiconductor layer overlapping with the gate electrode over the gate insulating layer, and a first wiring layer and a second wiring layer whose end portions overlap with the gate electrode over the first oxide semiconductor layer and in which a conductive layer and a second oxide semiconductor layer are stacked. Over the gate insulating layer, oxide semiconductor layers with different properties are bonded to each other, whereby stable operation can be performed as compared with Schottky junction. Thus, the junction leakage can be reduced and the characteristics of the non-linear element can be improved.
    Type: Application
    Filed: April 11, 2023
    Publication date: September 14, 2023
    Inventors: Shunpei YAMAZAKI, Kengo AKIMOTO, Shigeki KOMORI, Hideki UOCHI, Tomoya FUTAMURA, Takahiro KASAHARA
  • Patent number: 11695080
    Abstract: By using a conductive layer including Cu as a long lead wiring, increase in wiring resistance is suppressed. Further, the conductive layer including Cu is provided in such a manner that it does not overlap with the oxide semiconductor layer in which a channel region of a TFT is formed, and is surrounded by insulating layers including silicon nitride, whereby diffusion of Cu can be prevented; thus, a highly reliable semiconductor device can be manufactured. Specifically, a display device which is one embodiment of a semiconductor device can have high display quality and operate stably even when the size or definition thereof is increased.
    Type: Grant
    Filed: May 20, 2022
    Date of Patent: July 4, 2023
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Jun Koyama, Masahiro Takahashi, Hideyuki Kishida, Akiharu Miyanaga, Junpei Sugao, Hideki Uochi, Yasuo Nakamura
  • Publication number: 20230205028
    Abstract: It is an object of the present invention to apply a sufficient electrical field to a liquid crystal material in a horizontal electrical field liquid crystal display device typified by an FFS type. In a horizontal electrical field liquid crystal display, an electrical field is applied to a liquid crystal material right above a common electrode and a pixel electrode using plural pairs of electrodes rather than one pair of electrodes. One pair of electrodes includes a comb-shaped common electrode and a comb-shaped pixel electrode. Another pair of electrodes includes a common electrode provided in a pixel portion and the comb-shaped pixel electrode.
    Type: Application
    Filed: February 22, 2023
    Publication date: June 29, 2023
    Inventors: Hajime KIMURA, Hideki UOCHI
  • Publication number: 20230187453
    Abstract: A display device includes a pixel portion in which a pixel electrode layer is arranged in a matrix, and an inverted staggered thin film transistor having a combination of at least two kinds of oxide semiconductor layers with different amounts of oxygen is provided corresponding to the pixel electrode layer. In the periphery of the pixel portion in this display device, a pad portion is provided to be electrically connected to a common electrode layer formed on a counter substrate through a conductive layer made of the same material as the pixel electrode layer. One objection of our invention to prevent a defect due to separation of a thin film in various kinds of display devices is realized, by providing a structure suitable for a pad portion provided in a display panel.
    Type: Application
    Filed: February 6, 2023
    Publication date: June 15, 2023
    Inventors: Shunpei YAMAZAKI, Kengo AKIMOTO, Shigeki KOMORI, Hideki UOCHI, Rihito WADA, Yoko CHIBA
  • Publication number: 20230170345
    Abstract: A protective circuit includes a non-linear element which includes a gate electrode, a gate insulating layer covering the gate electrode, a first oxide semiconductor layer overlapping with the gate electrode over the gate insulating layer, a channel protective layer overlapping with a channel formation region of the first oxide semiconductor layer, and a pair of a first wiring layer and a second wiring layer whose end portions overlap with the gate electrode over the channel protective layer and in which a conductive layer and a second oxide semiconductor layer are stacked. Over the gate insulating layer, oxide semiconductor layers with different properties are bonded to each other, whereby stable operation can be performed as compared with Schottky junction. Thus, the junction leakage can be reduced and the characteristics of the non-linear element can be improved.
    Type: Application
    Filed: January 26, 2023
    Publication date: June 1, 2023
    Inventors: Shunpei YAMAZAKI, Kengo AKIMOTO, Shigeki KOMORI, Hideki UOCHI, Tomoya FUTAMURA, Takahiro KASAHARA
  • Patent number: 11646321
    Abstract: A protective circuit includes a non-linear element which includes a gate electrode, a gate insulating layer covering the gate electrode, a first oxide semiconductor layer overlapping with the gate electrode over the gate insulating layer, and a first wiring layer and a second wiring layer whose end portions overlap with the gate electrode over the first oxide semiconductor layer and in which a conductive layer and a second oxide semiconductor layer are stacked. Over the gate insulating layer, oxide semiconductor layers with different properties are bonded to each other, whereby stable operation can be performed as compared with Schottky junction. Thus, the junction leakage can be reduced and the characteristics of the non-linear element can be improved.
    Type: Grant
    Filed: July 1, 2021
    Date of Patent: May 9, 2023
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Kengo Akimoto, Shigeki Komori, Hideki Uochi, Tomoya Futamura, Takahiro Kasahara
  • Publication number: 20230138802
    Abstract: Disclosed is a semiconductor device having a memory cell which comprises a transistor having a control gate and a storage gate. The storage gate comprises an oxide semiconductor and is able to be a conductor and an insulator depending on the potential of the storage gate and the potential of the control gate. Data is written by setting the potential of the control gate to allow the storage gate to be a conductor, supplying a potential of data to be stored to the storage gate, and setting the potential of the control gate to allow the storage gate to be an insulator. Data is read by supplying a potential for reading to a read signal line connected to one of a source and a drain of the transistor and detecting the change in potential of a bit line connected to the other of the source and the drain.
    Type: Application
    Filed: December 30, 2022
    Publication date: May 4, 2023
    Inventors: Hideki UOCHI, Koichiro KAMATA
  • Publication number: 20230112113
    Abstract: A novel storage device is provided. The storage device includes a first wiring, a second wiring, and a first memory cell. The first memory cell includes a first transistor and a first magnetic tunnel junction device. One of a source or a drain of the first transistor is electrically connected to a first wiring. The other of the source or the drain of the first transistor is electrically connected to one terminal of the first magnetic tunnel junction device. Another terminal of the first magnetic tunnel junction device is electrically connected to the second wiring. The first transistor includes an oxide semiconductor in its channel formation region.
    Type: Application
    Filed: December 14, 2022
    Publication date: April 13, 2023
    Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.
    Inventors: Yoshiaki OIKAWA, Atsushi MIYAGUCHI, Hideki UOCHI
  • Patent number: 11610918
    Abstract: A display device includes a pixel portion in which a pixel electrode layer is arranged in a matrix, and an inverted staggered thin film transistor having a combination of at least two kinds of oxide semiconductor layers with different amounts of oxygen is provided corresponding to the pixel electrode layer. In the periphery of the pixel portion in this display device, a pad portion is provided to be electrically connected to a common electrode layer formed on a counter substrate through a conductive layer made of the same material as the pixel electrode layer. One objection of our invention to prevent a defect due to separation of a thin film in various kinds of display devices is realized, by providing a structure suitable for a pad portion provided in a display panel.
    Type: Grant
    Filed: December 5, 2019
    Date of Patent: March 21, 2023
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Kengo Akimoto, Shigeki Komori, Hideki Uochi, Rihito Wada, Yoko Chiba
  • Publication number: 20230066071
    Abstract: A novel image correction system is provided. The image correction system includes an imaging device, a first arithmetic device, a display portion including a plurality of pixels, and a second arithmetic device. The imaging device obtains imaging data by capturing a first-gray-level image displayed on the display portion. The first arithmetic device calculates the luminous intensity of each of the pixels and a correction standard by using the imaging data. The first arithmetic device calculates correction data for each of the pixels by using the luminous intensity and the correction standard. The second arithmetic device corrects a video signal by using the correction data. The display portion displays an image using the corrected video signal. The first arithmetic device calculates correction data for pixels that emit red light, pixels that emit green light, and pixels that emit blue light and modifies the correction data by using color temperature data.
    Type: Application
    Filed: August 24, 2022
    Publication date: March 2, 2023
    Inventors: Yusuke KOUMURA, Yuki OKAMOTO, Toshiki MIZUGUCHI, Tatsuya ONUKI, Hideki UOCHI
  • Patent number: 11592719
    Abstract: It is an object of the present invention to apply a sufficient electrical field to a liquid crystal material in a horizontal electrical field liquid crystal display device typified by an FFS type. In a horizontal electrical field liquid crystal display, an electrical field is applied to a liquid crystal material right above a common electrode and a pixel electrode using plural pairs of electrodes rather than one pair of electrodes. One pair of electrodes includes a comb-shaped common electrode and a comb-shaped pixel electrode. Another pair of electrodes includes a common electrode provided in a pixel portion and the comb-shaped pixel electrode.
    Type: Grant
    Filed: August 31, 2021
    Date of Patent: February 28, 2023
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Hajime Kimura, Hideki Uochi
  • Patent number: 11575013
    Abstract: A semiconductor device and the like with low power consumption are provided. In a semiconductor device including an electrostatic actuator group, an OS transistor and a capacitor are provided in each electrostatic actuator, and a power supply voltage supplied from the outside is boosted in each electrostatic actuator. The use of the OS transistor can retain the boosted voltage for a long period even after the supply of the power supply voltage is stopped. The use of the OS transistor can miniaturize the capacitor.
    Type: Grant
    Filed: October 22, 2019
    Date of Patent: February 7, 2023
    Assignee: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.
    Inventors: Kouhei Toyotaka, Hideki Uochi
  • Patent number: 11551751
    Abstract: Disclosed is a semiconductor device having a memory cell which comprises a transistor having a control gate and a storage gate. The storage gate comprises an oxide semiconductor and is able to be a conductor and an insulator depending on the potential of the storage gate and the potential of the control gate. Data is written by setting the potential of the control gate to allow the storage gate to be a conductor, supplying a potential of data to be stored to the storage gate, and setting the potential of the control gate to allow the storage gate to be an insulator. Data is read by supplying a potential for reading to a read signal line connected to one of a source and a drain of the transistor and detecting the change in potential of a bit line connected to the other of the source and the drain.
    Type: Grant
    Filed: May 20, 2020
    Date of Patent: January 10, 2023
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Hideki Uochi, Koichiro Kamata
  • Publication number: 20230005528
    Abstract: A novel memory device is provided. The memory device includes a plurality of memory cells, and one memory cell includes a first transistor and a second transistor. One of a source and a drain of the first transistor is electrically connected to a gate of the second transistor through a node SN. Data written through the first transistor is retained at the node SN. When an OS transistor is used as the first transistor, formation of a storage capacitor is not needed. A region with a low dielectric constant is provided outside the memory cell, whereby noise from the outside is reduced and stable operation is achieved.
    Type: Application
    Filed: September 8, 2022
    Publication date: January 5, 2023
    Inventors: Takahiko ISHIZU, Toshihiko SAITO, Hideki UOCHI, Shunpei YAMAZAKI