Patents by Inventor Hideki Uochi
Hideki Uochi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20230005528Abstract: A novel memory device is provided. The memory device includes a plurality of memory cells, and one memory cell includes a first transistor and a second transistor. One of a source and a drain of the first transistor is electrically connected to a gate of the second transistor through a node SN. Data written through the first transistor is retained at the node SN. When an OS transistor is used as the first transistor, formation of a storage capacitor is not needed. A region with a low dielectric constant is provided outside the memory cell, whereby noise from the outside is reduced and stable operation is achieved.Type: ApplicationFiled: September 8, 2022Publication date: January 5, 2023Inventors: Takahiko ISHIZU, Toshihiko SAITO, Hideki UOCHI, Shunpei YAMAZAKI
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Patent number: 11532340Abstract: A novel storage device is provided. The storage device includes a first wiring, a second wiring, and a first memory cell. The first memory cell includes a first transistor and a first magnetic tunnel junction device. One of a source or a drain of the first transistor is electrically connected to a first wiring. The other of the source or the drain of the first transistor is electrically connected to one terminal of the first magnetic tunnel junction device. Another terminal of the first magnetic tunnel junction device is electrically connected to the second wiring. The first transistor includes an oxide semiconductor in its channel formation region.Type: GrantFiled: May 21, 2021Date of Patent: December 20, 2022Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventors: Yoshiaki Oikawa, Atsushi Miyaguchi, Hideki Uochi
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Patent number: 11443796Abstract: A novel memory device is provided. The memory device includes a plurality of memory cells, and one memory cell includes a first transistor and a second transistor. One of a source and a drain of the first transistor is electrically connected to a gate of the second transistor through a node SN. Data written through the first transistor is retained at the node SN. When an OS transistor is used as the first transistor, formation of a storage capacitor is not needed. A region with a low dielectric constant is provided outside the memory cell, whereby noise from the outside is reduced and stable operation is achieved.Type: GrantFiled: June 13, 2019Date of Patent: September 13, 2022Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventors: Takahiko Ishizu, Toshihiko Saito, Hideki Uochi, Shunpei Yamazaki
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Publication number: 20220285556Abstract: By using a conductive layer including Cu as a long lead wiring, increase in wiring resistance is suppressed. Further, the conductive layer including Cu is provided in such a manner that it does not overlap with the oxide semiconductor layer in which a channel region of a TFT is formed, and is surrounded by insulating layers including silicon nitride, whereby diffusion of Cu can be prevented; thus, a highly reliable semiconductor device can be manufactured. Specifically, a display device which is one embodiment of a semiconductor device can have high display quality and operate stably even when the size or definition thereof is increased.Type: ApplicationFiled: May 20, 2022Publication date: September 8, 2022Inventors: Shunpei YAMAZAKI, Jun KOYAMA, Masahiro TAKAHASHI, Hideyuki KISHIDA, Akiharu MIYANAGA, Junpei SUGAO, Hideki UOCHI, Yasuo NAKAMURA
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Publication number: 20220262438Abstract: A highly reliable memory device is provided. On a side surface of a first conductor extending in a first direction, a first insulator, a first semiconductor, a second insulator, a second semiconductor, and a third insulator are provided in this order when seen from the first conductor side. The first conductor is provided with a first region overlapping with a second conductor with the first insulator, the first semiconductor, the second insulator, the second semiconductor, and the third insulator provided therebetween, and a second region overlapping with a third conductor with the first insulator, the first semiconductor, the second insulator, the second semiconductor, and the third insulator provided therebetween. In the second region, a fourth conductor is provided between the first insulator and the first semiconductor.Type: ApplicationFiled: July 22, 2020Publication date: August 18, 2022Inventors: Shunpei YAMAZAKI, Hajime KIMURA, Takanori MATSUZAKI, Tatsuya ONUKI, Yuki OKAMOTO, Hideki UOCHI, Satoru OKAMOTO
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Publication number: 20220262858Abstract: A highly reliable memory device is provided. On a side surface of a first conductor extending in a first direction, a first insulator, a first semiconductor, a second insulator, a second semiconductor, and a third insulator are provided in this order when seen from the first conductor side. A first region overlapping with a second conductor with the first insulator, the first semiconductor, the second insulator, the second semiconductor, and the third insulator therebetween, and a second region overlapping with a third conductor with the first insulator, the first semiconductor, the second insulator, the second semiconductor, and the third insulator therebetween are provided in the first conductor. In the second region, a fourth conductor is provided between the first insulator and the first semiconductor.Type: ApplicationFiled: July 31, 2020Publication date: August 18, 2022Inventors: Shunpei YAMAZAKI, Hajime KIMURA, Takanori MATSUZAKI, Tatsuya ONUKI, Yuki OKAMOTO, Hideki UOCHI, Satoru OKAMOTO, Hiromichi GODO, Kazuki TSUDA, Hitoshi KUNITAKE
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Publication number: 20220231056Abstract: A protective circuit includes a non-linear element, which includes a gate electrode, a gate insulating layer covering the gate electrode, a pair of first and second wiring layers whose end portions overlap with the gate electrode over the gate insulating layer and in which a second oxide semiconductor layer and a conductive layer are stacked, and a first oxide semiconductor layer which overlaps with at least the gate electrode and which is in contact with the gate insulating layer, side face portions and part of top face portions of the conductive layer and side face portions of the second oxide semiconductor layer in the first wiring layer and the second wiring layer. Over the gate insulating layer, oxide semiconductor layers with different properties are bonded to each other, whereby stable operation can be performed as compared with Schottky junction. Thus, the junction leakage can be decreased and the characteristics of the non-linear element can be improved.Type: ApplicationFiled: April 11, 2022Publication date: July 21, 2022Inventors: Shunpei YAMAZAKI, Kengo AKIMOTO, Shigeki KOMORI, Hideki UOCHI, Tomoya FUTAMURA, Takahiro KASAHARA
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Patent number: 11367793Abstract: By using a conductive layer including Cu as a long lead wiring, increase in wiring resistance is suppressed. Further, the conductive layer including Cu is provided in such a manner that it does not overlap with the oxide semiconductor layer in which a channel region of a TFT is formed, and is surrounded by insulating layers including silicon nitride, whereby diffusion of Cu can be prevented; thus, a highly reliable semiconductor device can be manufactured. Specifically, a display device which is one embodiment of a semiconductor device can have high display quality and operate stably even when the size or definition thereof is increased.Type: GrantFiled: September 1, 2020Date of Patent: June 21, 2022Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventors: Shunpei Yamazaki, Jun Koyama, Masahiro Takahashi, Hideyuki Kishida, Akiharu Miyanaga, Junpei Sugao, Hideki Uochi, Yasuo Nakamura
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Publication number: 20220037475Abstract: A semiconductor device and the like with low power consumption are provided. In a semiconductor device including an electrostatic actuator group, an OS transistor and a capacitor are provided in each electrostatic actuator, and a power supply voltage supplied from the outside is boosted in each electrostatic actuator. The use of the OS transistor can retain the boosted voltage for a long period even after the supply of the power supply voltage is stopped. The use of the OS transistor can miniaturize the capacitor.Type: ApplicationFiled: October 22, 2019Publication date: February 3, 2022Inventors: Kouhei TOYOTAKA, Hideki UOCHI
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Publication number: 20220020841Abstract: A display device includes a pixel portion in which a pixel is arranged in a matrix, the pixel including an inverted staggered thin film transistor having a combination of at least two kinds of oxide semiconductor layers with different amounts of oxygen and having a channel protective layer over a semiconductor layer to be a channel formation region overlapping a gate electrode layer and a pixel electrode layer electrically connected to the inverted staggered thin film transistor. In the periphery of the pixel portion in this display device, a pad portion including a conductive layer made of the same material as the pixel electrode layer is provided. In addition, the conductive layer is electrically connected to a common electrode layer formed on a counter substrate.Type: ApplicationFiled: September 29, 2021Publication date: January 20, 2022Inventors: Shunpei YAMAZAKI, Kengo AKIMOTO, Shigeki KOMORI, Hideki UOCHI, Rihito WADA, Yoko CHIBA
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Publication number: 20210397029Abstract: It is an object of the present invention to apply a sufficient electrical field to a liquid crystal material in a horizontal electrical field liquid crystal display device typified by an FFS type. In a horizontal electrical field liquid crystal display, an electrical field is applied to a liquid crystal material right above a common electrode and a pixel electrode using plural pairs of electrodes rather than one pair of electrodes. One pair of electrodes includes a comb-shaped common electrode and a comb-shaped pixel electrode. Another pair of electrodes includes a common electrode provided in a pixel portion and the comb-shaped pixel electrode.Type: ApplicationFiled: August 31, 2021Publication date: December 23, 2021Inventors: Hajime KIMURA, Hideki UOCHI
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Publication number: 20210356784Abstract: A highly reliable display device is provided. In a flexible display device including at least a first display region and a second display region, at least a portion of a wiring provided in the first display region or the second display region has a meandering shape or a chain-like shape. Since the wiring has a meandering shape or a chain-like shape, a short-circuit, a disconnection, or the like of the wiring due to curving or bending of the display device does not occur easily. The wiring having a meandering shape or a chain-like shape can prevent defective operation, lowered reliability, or the like of the display device.Type: ApplicationFiled: July 28, 2021Publication date: November 18, 2021Inventors: Shunpei YAMAZAKI, Daisuke KUBOTA, Hideki UOCHI
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Publication number: 20210327916Abstract: A protective circuit includes a non-linear element which includes a gate electrode, a gate insulating layer covering the gate electrode, a first oxide semiconductor layer overlapping with the gate electrode over the gate insulating layer, and a first wiring layer and a second wiring layer whose end portions overlap with the gate electrode over the first oxide semiconductor layer and in which a conductive layer and a second oxide semiconductor layer are stacked. Over the gate insulating layer, oxide semiconductor layers with different properties are bonded to each other, whereby stable operation can be performed as compared with Schottky junction. Thus, the junction leakage can be reduced and the characteristics of the non-linear element can be improved.Type: ApplicationFiled: July 1, 2021Publication date: October 21, 2021Inventors: Shunpei YAMAZAKI, Kengo AKIMOTO, Shigeki KOMORI, Hideki UOCHI, Tomoya FUTAMURA, Takahiro KASAHARA
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Patent number: 11152397Abstract: A protective circuit includes a non-linear element which includes a gate electrode, a gate insulating layer covering the gate electrode, a first oxide semiconductor layer overlapping with the gate electrode over the gate insulating layer, and a first wiring layer and a second wiring layer whose end portions overlap with the gate electrode over the first oxide semiconductor layer and in which a conductive layer and a second oxide semiconductor layer are stacked. Over the gate insulating layer, oxide semiconductor layers with different properties are bonded to each other, whereby stable operation can be performed as compared with Schottky junction. Thus, the junction leakage can be reduced and the characteristics of the non-linear element can be improved.Type: GrantFiled: November 21, 2019Date of Patent: October 19, 2021Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventors: Shunpei Yamazaki, Kengo Akimoto, Shigeki Komori, Hideki Uochi, Tomoya Futamura, Takahiro Kasahara
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Patent number: 11139359Abstract: A display device includes a pixel portion in which a pixel is arranged in a matrix, the pixel including an inverted staggered thin film transistor having a combination of at least two kinds of oxide semiconductor layers with different amounts of oxygen and having a channel protective layer over a semiconductor layer to be a channel formation region overlapping a gate electrode layer and a pixel electrode layer electrically connected to the inverted staggered thin film transistor. In the periphery of the pixel portion in this display device, a pad portion including a conductive layer made of the same material as the pixel electrode layer is provided. In addition, the conductive layer is electrically connected to a common electrode layer formed on a counter substrate.Type: GrantFiled: October 18, 2016Date of Patent: October 5, 2021Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventors: Shunpei Yamazaki, Kengo Akimoto, Shigeki Komori, Hideki Uochi, Rihito Wada, Yoko Chiba
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Patent number: 11126053Abstract: It is an object of the present invention to apply a sufficient electrical field to a liquid crystal material in a horizontal electrical field liquid crystal display device typified by an FFS type. In a horizontal electrical field liquid crystal display, an electrical field is applied to a liquid crystal material right above a common electrode and a pixel electrode using plural pairs of electrodes rather than one pair of electrodes. One pair of electrodes includes a comb-shaped common electrode and a comb-shaped pixel electrode. Another pair of electrodes includes a common electrode provided in a pixel portion and the comb-shaped pixel electrode.Type: GrantFiled: January 7, 2020Date of Patent: September 21, 2021Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventors: Hajime Kimura, Hideki Uochi
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Publication number: 20210288210Abstract: An object is to provide a semiconductor device including a thin film transistor with excellent electrical characteristics and high reliability and a method for manufacturing the semiconductor device with high mass productivity. A main point is to form a low-resistance oxide semiconductor layer as a source or drain region after forming a drain or source electrode layer over a gate insulating layer and to foiiii an oxide semiconductor film thereover as a semiconductor layer. It is preferable that an oxygen-excess oxide semiconductor layer be used as a semiconductor layer and an oxygen-deficient oxide semiconductor layer be used as a source region and a drain region.Type: ApplicationFiled: May 28, 2021Publication date: September 16, 2021Inventors: Shunpei YAMAZAKI, Kengo AKIMOTO, Shigeki KOMORI, Hideki UOCHI
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Publication number: 20210272614Abstract: A novel storage device is provided. The storage device includes a first wiring, a second wiring, and a first memory cell. The first memory cell includes a first transistor and a first magnetic tunnel junction device. One of a source or a drain of the first transistor is electrically connected to a first wiring. The other of the source or the drain of the first transistor is electrically connected to one terminal of the first magnetic tunnel junction device. Another terminal of the first magnetic tunnel junction device is electrically connected to the second wiring. The first transistor includes an oxide semiconductor in its channel formation region.Type: ApplicationFiled: May 21, 2021Publication date: September 2, 2021Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.Inventors: Yoshiaki OIKAWA, Atsushi MIYAGUCHI, Hideki UOCHI
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Patent number: 11106099Abstract: A highly reliable display device is provided. In a flexible display device including at least a first display region and a second display region, at least a portion of a wiring provided in the first display region or the second display region has a meandering shape or a chain-like shape. Since the wiring has a meandering shape or a chain-like shape, a short-circuit, a disconnection, or the like of the wiring due to curving or bending of the display device does not occur easily. The wiring having a meandering shape or a chain-like shape can prevent defective operation, lowered reliability, or the like of the display device.Type: GrantFiled: June 15, 2017Date of Patent: August 31, 2021Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventors: Shunpei Yamazaki, Daisuke Kubota, Hideki Uochi
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Publication number: 20210257020Abstract: A novel memory device is provided. The memory device includes a plurality of memory cells, and one memory cell includes a first transistor and a second transistor. One of a source and a drain of the first transistor is electrically connected to a gate of the second transistor through a node SN. Data written through the first transistor is retained at the node SN. When an OS transistor is used as the first transistor, formation of a storage capacitor is not needed. A region with a low dielectric constant is provided outside the memory cell, whereby noise from the outside is reduced and stable operation is achieved.Type: ApplicationFiled: June 13, 2019Publication date: August 19, 2021Inventors: Takahiko ISHIZU, Toshihiko SAITO, Hideki UOCHI, Shunpei YAMAZAKI