Patents by Inventor Hideki Yamada
Hideki Yamada has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20250030949Abstract: A visible light communication method transmits a signal by visible light communication. The visible light communication method includes modulating the signal into a predetermined blinking pattern, and transmitting the signal by causing visible light to blink according to the predetermined blinking pattern and toward a wall, from a projector disposed in an indoor space surrounded by the wall. The visible light communication method also includes projecting video from the projector toward the wall, wherein the visible light is reflected by the wall to prevent the signal from being received outside of the indoor space, and the signal is used to transmit data related to the video projected to a terminal in the indoor space.Type: ApplicationFiled: July 24, 2024Publication date: January 23, 2025Applicant: PANASONIC INTELLECTUAL PROPERTY CORPORATION OF AMERICAInventors: Mitsuaki OSHIMA, Koji NAKANISHI, Hideki AOYAMA, Ikuo FUCHIGAMI, Hidehiko SHIN, Tsutomu MUKAI, Yosuke MATSUSHITA, Shigehiro IIDA, Kazunori YAMADA
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Patent number: 12202079Abstract: A welding device for a plate laminated body according to an embodiment includes a welding torch, a chuck for gripping a plurality of laminated plates with a lamination direction being in a horizontal position, and at least one support extending along the lamination direction for supporting the plate laminated body from below.Type: GrantFiled: June 11, 2019Date of Patent: January 21, 2025Assignee: MAYEKAWA MFG. CO., LTD.Inventors: Keisuke Yamada, Tetsuji Terada, Daisuke Miyazaki, Hideki Shudai
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Publication number: 20250021106Abstract: A moving object control apparatus in the present disclosure that adjusts a stop position of a moving object based on an instruction of a user, acquires instruction information of the user and acquires a captured image captured in a moving object. The apparatus determines a stop position of the moving object and controls traveling of the moving object to cause the moving object to travel toward the determined stop position. The apparatus (i) determines a first stop position using position information of a communication device used by the user or position information corresponding to a destination included in first instruction information of the user, and (ii) determines a second stop position based on second instruction information of the user and a region of a predetermined target identified in the captured image.Type: ApplicationFiled: September 26, 2024Publication date: January 16, 2025Applicant: HONDA MOTOR CO., LTD.Inventors: Kentaro YAMADA, Yuji YASUI, Nanami TSUKAMOTO, Naoki HOSOMI, Anirudh Reddy KONDAPALLY, Kosuke NAKANISHI, Hideki MATSUNAGA, Aman JAIN
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Publication number: 20250022498Abstract: A first circuit outputs first information indicating presence/absence of a magnetic wall between two adjacent portions among portions of a magnetic body, and second information based on the combination of magnetization states of the two portions. A first storage circuit stores first bits corresponding to the portions. A most significant bit of the first bits has a value independent of a magnetization state of a corresponding one of the portions, and the first bits have a value based on the first information. A second storage circuit stores the second information. The second circuit causes the first storage circuit to output the first bits when a value of a least significant bit of the first bits matches a value of the second information, and otherwise third bits having inverse values of the first bits.Type: ApplicationFiled: July 5, 2024Publication date: January 16, 2025Applicant: Kioxia CorporationInventors: Shogo MUTO, Masanobu SHIRAKAWA, Hideki YAMADA, Ryo YAMAKI, Yoshihiro UEDA, Tsuyoshi KONDO
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Patent number: 12190960Abstract: According to one embodiment, a memory system includes a semiconductor memory device and a controller. The semiconductor memory device includes a first memory cell configured to store data. The controller is configured to output a first parameter and a first command. The first parameter relates to an erase voltage for a first erase operation with respect to the first memory cell. The first command instructs the first erase operation. The controller outputs the first command after outputting the first parameter to the semiconductor memory device.Type: GrantFiled: October 28, 2022Date of Patent: January 7, 2025Assignee: Kioxia CorporationInventors: Kengo Kurose, Masanobu Shirakawa, Hideki Yamada, Marie Takada
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Patent number: 12002515Abstract: A memory device includes a first block including a first memory cell and a first word line connected to the first memory cell, a second block including a second memory cell and a second word line connected to the second memory cell, and a control circuit. The control circuit applies a first voltage to each of the first and second word lines to supply a first erase pulse having a first erase intensity to each of the first and second blocks, when a first erase operation is executed, and applies the first voltage to the first word line and a second voltage higher than the first voltage to the second word line, to supply the first erase pulse to the first block and a second erase pulse having a second erase intensity less than the first erase intensity to the second block, when a second erase operation is executed.Type: GrantFiled: March 3, 2022Date of Patent: June 4, 2024Assignee: Kioxia CorporationInventors: Takumi Fujimori, Tetsuya Sunata, Masanobu Shirakawa, Hideki Yamada
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Publication number: 20230420067Abstract: A memory system includes a nonvolatile memory including memory cells each configured to store first and second bits, and a memory controller. The memory controller is configured to: read first data by using a first voltage to a first read process that reads data corresponding to the first bit from the memory cells; read second data by using a second voltage to a second read process that reads data corresponding to the second bit from the memory cells; in a case where an error correction process of the first data is successful, determine a third voltage, based on the first data and third data that is obtained by error-correcting the first data; and update a first read voltage that is used to the first read process, from the first voltage to the third voltage.Type: ApplicationFiled: November 9, 2022Publication date: December 28, 2023Applicant: Kioxia CorporationInventors: Marie TAKADA, Masanobu SHIRAKAWA, Hideki YAMADA, Ryo YAMAKI
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Publication number: 20230395178Abstract: A memory system according to an embodiment includes a memory device, and a memory controller. The memory device includes first and second memory cells, a first word line, and first and second bit lines. The first and second memory cells are provided in first and second layers, respectively. The first word line is coupled to the first memory cell and the second memory cell. The first bit line is coupled to the first memory cell. The second bit line is coupled to the second memory cell. The memory controller includes a storage circuit capable of storing a correction value table. The correction value table is configured to store a first correction value of a read voltage associated with the first layer and a second correction voltage of a read voltage associated with the second layer.Type: ApplicationFiled: August 22, 2023Publication date: December 7, 2023Applicant: KIOXIA CORPORATIONInventors: Masanobu SHIRAKAWA, Hideki YAMADA, Marie TAKADA
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Patent number: 11797232Abstract: A memory controller according to an embodiment includes a control circuit configured to duplicate and store data received from an external host device. The control circuit is configured to, when a write request specifying first data and a first logical address is received: i) allocate a first physical address corresponding to a first bit to the first logical address, and order a first memory device to write the first data to the first physical address; and ii) allocate a first mirroring physical address corresponding to a second bit to the first physical address, and order a second memory device to write the first data to the first mirroring physical address. A number of reads the first bit is different from a number of reads for the second bit.Type: GrantFiled: March 15, 2022Date of Patent: October 24, 2023Assignee: Kioxia CorporationInventors: Hideki Yamada, Masanobu Shirakawa, Naomi Takeda
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Patent number: 11776651Abstract: A memory system according to an embodiment includes a memory device, and a memory controller. The memory device includes first and second memory cells, a first word line, and first and second bit lines. The first and second memory cells are provided in first and second layers, respectively. The first word line is coupled to the first memory cell and the second memory cell. The first bit line is coupled to the first memory cell. The second bit line is coupled to the second memory cell. The memory controller includes a storage circuit capable of storing a correction value table. The correction value table is configured to store a first correction value of a read voltage associated with the first layer and a second correction voltage of a read voltage associated with the second layer.Type: GrantFiled: March 16, 2021Date of Patent: October 3, 2023Assignee: Kioxia CorporationInventors: Masanobu Shirakawa, Hideki Yamada, Marie Takada
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Patent number: 11755236Abstract: According to one embodiment, a shift register memory writes data having a first size corresponding to a capacity of a block to a plurality of layers of a plurality of data storing shift strings included in the block, in response to a first command sequence specifying a first write mode from a controller. In response to a second command sequence specifying a second write mode from the controller, the shift register memory writes data having a second size smaller than the capacity of the block to the plurality of layers of one or more first data storing shift strings of the plurality of data storing shift strings, without writing data to each of other data storing shift strings except the one or more first data storing shift strings.Type: GrantFiled: March 15, 2021Date of Patent: September 12, 2023Assignee: Kioxia CorporationInventors: Kengo Kurose, Masanobu Shirakawa, Naomi Takeda, Hideki Yamada
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Patent number: 11742026Abstract: In connection with a write operation, a memory controller transmits a first command sequence to a memory chip, thereby causing the memory chip to execute a first-stage program operation that includes a first operation and a first part of a second operation after the first operation, and a second command sequence to the memory chip after the first-stage program operation is executed, thereby causing the memory chip to execute a second-stage program operation that includes a second part of the second operation and no part of the first operation. During the first operation, a program voltage is applied a plurality of times while increasing the program voltage each of the times by a first step size. During the second operation, the program voltage is applied a plurality of times while increasing the program voltage each of the times by a second step size smaller than the first step size.Type: GrantFiled: July 20, 2022Date of Patent: August 29, 2023Assignee: Kioxia CorporationInventors: Hideki Yamada, Marie Takada, Masanobu Shirakawa
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Patent number: 11731256Abstract: Provided is an electric tool with which work efficiency can be improved. A controller of an electric tool can execute: a first control, whereby during a non-operating state after a motor has started up and before a tip tool is set to be in an operating state, the motor is driven at a slow idling rotation speed, and when the tip tool is set to be in the operating state, the motor is driven at a normal rotation speed which is higher than the slow idling rotation speed; and a second control, whereby in a case where a trigger switch has been turned off in a state where the motor is being driven at the normal rotation speed and the trigger switch is thereafter turned on again under a prescribed condition, the motor is driven at the normal rotation speed regardless of the state of the tip tool.Type: GrantFiled: August 31, 2018Date of Patent: August 22, 2023Assignee: Koki Holdings Co., Ltd.Inventors: Hideki Yamada, Hideyuki Hashimoto, Yuta Noguchi
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Publication number: 20230213348Abstract: According to one embodiment, an information processing device includes: a first memory; a first receiver; a first determination section; and a first transmitter. The first memory is configured to store first image data of interior of a vehicle at a first point in time. The first receiver is configured to receive second image data of the interior of the vehicle at a second point of time from the vehicle. The first determination section is configured to determine whether a change has been caused in the interior of the vehicle between the first point in time and the second point in time. The first transmitter is configured to transmit first data based on the determination result.Type: ApplicationFiled: March 6, 2023Publication date: July 6, 2023Applicant: KIOXIA CORPORATIONInventors: Hideki YAMADA, Masanobu SHIRAKAWA, Marie KURONAGA
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Patent number: 11692538Abstract: A compressor system includes: a first compressor including a first casing having a cylindrical shape, and a first bundle capable of being inserted into and pulled out from the first casing in an axial direction of the first casing; and a second compressor including a second casing having a cylindrical shape, and a second bundle capable of being inserted into and pulled out from the second casing in an axial direction of the second casing. The first and second compressors are arranged to face each other to cause pullout directions of the respective bundles to be opposite to each other. A maintenance space shareable for insertion and pullout operations of the first bundle and insertion and pullout operations of the second bundle is interposed between the first bundle and the second bundle, and is available for the bundle under the insertion and pullout operations.Type: GrantFiled: June 11, 2021Date of Patent: July 4, 2023Assignee: MITSUBISHI HEAVY INDUSTRIES COMPRESSOR CORPORATIONInventors: Takuya Kinoshita, Hideki Yamada
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Publication number: 20230137055Abstract: An inverter is disposed adjacent to a motor. The inverter includes a plurality of power modules, a smoothing capacitor, and busbars connecting the power modules and the smoothing capacitor. The plurality of power modules are disposed to be arranged along the periphery of the smoothing capacitor. The smoothing capacitor is disposed at a central portion of the inverter and also disposed in the inner portion of the inverter such that the smoothing capacitor and each of the power modules are arranged on the same plane.Type: ApplicationFiled: October 21, 2022Publication date: May 4, 2023Inventors: Takayuki Sato, Akihiro Noda, Hiroaki Kashihara, Hideki Yamada, Hideki Hosoya, Masashi Hayashiguchi
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Patent number: 11625926Abstract: According to one embodiment, an information processing device includes: a first memory; a first receiver; a first determination section; and a first transmitter. The first memory is configured to store first image data of interior of a vehicle at a first point in time. The first receiver is configured to receive second image data of the interior of the vehicle at a second point of time from the vehicle. The first determination section is configured to determine whether a change has been caused in the interior of the vehicle between the first point in time and the second point in time. The first transmitter is configured to transmit first data based on the determination result.Type: GrantFiled: September 11, 2019Date of Patent: April 11, 2023Assignee: KIOXIA CORPORATIONInventors: Hideki Yamada, Masanobu Shirakawa, Marie Kuronaga
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Publication number: 20230087010Abstract: A memory controller according to an embodiment includes a control circuit configured to duplicate and store data received from an external host device. The control circuit is configured to, when a write request specifying first data and a first logical address is received: i) allocate a first physical address corresponding to a first bit to the first logical address, and order a first memory device to write the first data to the first physical address; and ii) allocate a first mirroring physical address corresponding to a second bit to the first physical address, and order a second memory device to write the first data to the first mirroring physical address. A number of reads the first bit is different from a number of reads for the second bit.Type: ApplicationFiled: March 15, 2022Publication date: March 23, 2023Applicant: Kioxia CorporationInventors: Hideki YAMADA, Masanobu SHIRAKAWA, Naomi TAKEDA
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Publication number: 20230090202Abstract: A memory device includes a first block including a first memory cell and a first word line connected to the first memory cell, a second block including a second memory cell and a second word line connected to the second memory cell, and a control circuit. The control circuit applies a first voltage to each of the first and second word lines to supply a first erase pulse having a first erase intensity to each of the first and second blocks, when a first erase operation is executed, and applies the first voltage to the first word line and a second voltage higher than the first voltage to the second word line, to supply the first erase pulse to the first block and a second erase pulse having a second erase intensity less than the first erase intensity to the second block, when a second erase operation is executed.Type: ApplicationFiled: March 3, 2022Publication date: March 23, 2023Inventors: Takumi FUJIMORI, Tetsuya SUNATA, Masanobu SHIRAKAWA, Hideki YAMADA
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Publication number: 20230047861Abstract: According to one embodiment, a memory system includes a semiconductor memory device and a controller. The semiconductor memory device includes a first memory cell configured to store data. The controller is configured to output a first parameter and a first command. The first parameter relates to an erase voltage for a first erase operation with respect to the first memory cell. The first command instructs the first erase operation. The controller outputs the first command after outputting the first parameter to the semiconductor memory device.Type: ApplicationFiled: October 28, 2022Publication date: February 16, 2023Applicant: Kioxia CorporationInventors: Kengo KUROSE, Masanobu SHIRAKAWA, Hideki YAMADA, Marie TAKADA