Patents by Inventor Hideki Yamada
Hideki Yamada has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11514986Abstract: According to one embodiment, a memory system includes a semiconductor memory device and a controller. The semiconductor memory device includes a first memory cell configured to store data. The controller is configured to output a first parameter and a first command. The first parameter relates to an erase voltage for a first erase operation with respect to the first memory cell. The first command instructs the first erase operation. The controller outputs the first command after outputting the first parameter to the semiconductor memory device.Type: GrantFiled: March 16, 2021Date of Patent: November 29, 2022Assignee: Kioxia CorporationInventors: Kengo Kurose, Masanobu Shirakawa, Hideki Yamada, Marie Takada
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Patent number: 11501839Abstract: A memory system includes a semiconductor storage device including a memory cell array including a plurality of groups of memory cells, and a control circuit configured to perform, upon receipt of a write command, a write operation on one of the groups of memory cells, and a memory controller is configured to, when transmitting the write command to perform the write operation on the one of the groups of memory cells, determine a first write voltage value for the write operation based on a total number of write operations or erase operations that have been performed on the one of the groups of memory cells, and transmit the write command to the semiconductor storage device together with the determined first write voltage value.Type: GrantFiled: March 2, 2021Date of Patent: November 15, 2022Assignee: KIOXIA CORPORATIONInventors: Hideki Yamada, Masanobu Shirakawa
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Publication number: 20220351780Abstract: In connection with a write operation, a memory controller transmits a first command sequence to a memory chip, thereby causing the memory chip to execute a first-stage program operation that includes a first operation and a first part of a second operation after the first operation, and a second command sequence to the memory chip after the first-stage program operation is executed, thereby causing the memory chip to execute a second-stage program operation that includes a second part of the second operation and no part of the first operation. During the first operation, a program voltage is applied a plurality of times while increasing the program voltage each of the times by a first step size. During the second operation, the program voltage is applied a plurality of times while increasing the program voltage each of the times by a second step size smaller than the first step size.Type: ApplicationFiled: July 20, 2022Publication date: November 3, 2022Inventors: Hideki YAMADA, Marie TAKADA, Masanobu SHIRAKAWA
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Patent number: 11430520Abstract: In connection with a write operation, a memory controller transmits a first command sequence to a memory chip, thereby causing the memory chip to execute a first-stage program operation that includes a first operation and a first part of a second operation after the first operation, and a second command sequence to the memory chip after the first-stage program operation is executed, thereby causing the memory chip to execute a second-stage program operation that includes a second part of the second operation and no part of the first operation. During the first operation, a program voltage is applied a plurality of times while increasing the program voltage each of the times by a first step size. During the second operation, the program voltage is applied a plurality of times while increasing the program voltage each of the times by a second step size smaller than the first step size.Type: GrantFiled: February 26, 2020Date of Patent: August 30, 2022Assignee: KIOXIA CORPORATIONInventors: Hideki Yamada, Marie Takada, Masanobu Shirakawa
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Patent number: 11347584Abstract: A memory system controls a shift register memory and writes encoded data including a plurality of error correction code frames into a block of the shift register memory. The memory system is configured to store, into a location corresponding to a first layer in a first data storing shift string, first data included in a first error correction code frame, to store, into a location corresponding to a second layer in the first data storing shift string, second data included in a second error correction code frame, and to store, into a location corresponding to the second layer in a second data storing shift string, third data included in the first error correction code frame.Type: GrantFiled: March 3, 2020Date of Patent: May 31, 2022Assignee: Kioxia CorporationInventors: Masanobu Shirakawa, Hideki Yamada, Marie Takada, Ryo Yamaki, Osamu Torii, Naomi Takeda
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Patent number: 11325130Abstract: A multiwell instrument includes a vessel having an inside; a plurality of culture plates arranged in the inside of the vessel, each individual one of the plurality of culture plates having an inside in which material to be examined can be stored; and filters disposed inside the respective culture plates to partition the insides of the respective culture plates into at least two wells which are horizontally adjacent.Type: GrantFiled: February 10, 2017Date of Patent: May 10, 2022Assignees: GINREILAB INC., SHINKO CHEMICAL CO., LTD.Inventors: Takeo Shimasaki, Yumiko Kitano, Hideki Yamada
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Publication number: 20220093199Abstract: A memory system according to an embodiment includes a memory device, and a memory controller. The memory device includes first and second memory cells, a first word line, and first and second bit lines. The first and second memory cells are provided in first and second layers, respectively. The first word line is coupled to the first memory cell and the second memory cell. The first bit line is coupled to the first memory cell. The second bit line is coupled to the second memory cell. The memory controller includes a storage circuit capable of storing a correction value table. The correction value table is configured to store a first correction value of a read voltage associated with the first layer and a second correction voltage of a read voltage associated with the second layer.Type: ApplicationFiled: March 16, 2021Publication date: March 24, 2022Applicant: Kioxia CorporationInventors: Masanobu SHIRAKAWA, Hideki YAMADA, Marie TAKADA
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Publication number: 20220066688Abstract: According to one embodiment, a shift register memory writes data having a first size corresponding to a capacity of a block to a plurality of layers of a plurality of data storing shift strings included in the block, in response to a first command sequence specifying a first write mode from a controller. In response to a second command sequence specifying a second write mode from the controller, the shift register memory writes data having a second size smaller than the capacity of the block to the plurality of layers of one or more first data storing shift strings of the plurality of data storing shift strings, without writing data to each of other data storing shift strings except the one or more first data storing shift strings.Type: ApplicationFiled: March 15, 2021Publication date: March 3, 2022Applicant: Kioxia CorporationInventors: Kengo KUROSE, Masanobu SHIRAKAWA, Naomi TAKEDA, Hideki YAMADA
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Publication number: 20220068402Abstract: According to the one embodiment, a memory system includes a semiconductor memory device and a memory controller. The semiconductor memory device includes: first and second memory cells stacked above a substrate; a first word line coupled to the first and second memory cells; a first bit line coupled to the first memory cell; and a second bit line coupled to the second memory cell. A first state read operation includes a first read operation for reading data from the first memory cell and a second read operation for reading data from the second memory cell. A first read voltage is applied to the first word line during a first period for executing the first read operation, and a second read voltage is applied to the first word line during a second period for executing the second read operation.Type: ApplicationFiled: March 3, 2021Publication date: March 3, 2022Applicant: Kioxia CorporationInventors: Hideki YAMADA, Masanobu SHIRAKAWA
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Publication number: 20220056899Abstract: A compressor system includes: a first compressor including a first casing having a cylindrical shape, and a first bundle capable of being inserted into and pulled out from the first casing in an axial direction of the first casing; and a second compressor including a second casing having a cylindrical shape, and a second bundle capable of being inserted into and pulled out from the second casing in an axial direction of the second casing. The first and second compressors are arranged to face each other to cause pullout directions of the respective bundles to be opposite to each other. A maintenance space shareable for insertion and pullout operations of the first bundle and insertion and pullout operations of the second bundle is interposed between the first bundle and the second bundle, and is available for the bundle under the insertion and pullout operations.Type: ApplicationFiled: June 11, 2021Publication date: February 24, 2022Applicant: MITSUBISHI HEAVY INDUSTRIES COMPRESSOR CORPORATIONInventors: Takuya Kinoshita, Hideki Yamada
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Publication number: 20220028460Abstract: According to one embodiment, a memory system includes a semiconductor memory device and a controller. The semiconductor memory device includes a first memory cell configured to store data. The controller is configured to output a first parameter and a first command. The first parameter relates to an erase voltage for a first erase operation with respect to the first memory cell. The first command instructs the first erase operation. The controller outputs the first command after outputting the first parameter to the semiconductor memory device.Type: ApplicationFiled: March 16, 2021Publication date: January 27, 2022Applicant: Kioxia CorporationInventors: Kengo KUROSE, Masanobu SHIRAKAWA, Hideki YAMADA, Marie TAKADA
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Publication number: 20210324877Abstract: A suspending tool includes a suspending tool main body that extends to be parallel with an axial direction above a rotor main body, a pair of bearing supporting portions that are disposed at an interval in the axial direction and are detachable from the bearing portions, a pair of seal supporting portions that are disposed inside the pair of bearing supporting portions in the axial direction at an interval in the axial direction and are detachable from the seal portions, and a plurality of diaphragm supporting portions that are disposed inside the pair of seal supporting portions in the axial direction such that the diaphragm supporting portions are disposed at intervals in the axial direction and are detachable from the diaphragms.Type: ApplicationFiled: March 16, 2021Publication date: October 21, 2021Applicant: MITSUBISHI HEAVY INDUSTRIES COMPRESSOR CORPORATIONInventor: Hideki Yamada
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Publication number: 20210183455Abstract: A memory system includes a semiconductor storage device including a memory cell array including a plurality of groups of memory cells, and a control circuit configured to perform, upon receipt of a write command, a write operation on one of the groups of memory cells, and a memory controller is configured to, when transmitting the write command to perform the write operation on the one of the groups of memory cells, determine a first write voltage value for the write operation based on a total number of write operations or erase operations that have been performed on the one of the groups of memory cells, and transmit the write command to the semiconductor storage device together with the determined first write voltage value.Type: ApplicationFiled: March 2, 2021Publication date: June 17, 2021Inventors: Hideki YAMADA, Masanobu SHIRAKAWA
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Patent number: 11037643Abstract: According to one embodiment, a magnetic memory puts a first magnetic domain having a magnetization direction which is the same as or opposite to a magnetic domain of a first layer of a magnetic memory line, into the first layer, based on a value of data and the magnetization direction of the first layer. When receiving a first command, the magnetic memory puts a first additional magnetic domain and a second additional magnetic domain having a magnetization direction opposite to the first additional magnetic domain into the magnetic memory line. When receiving a second command, the magnetic memory read the first and second additional magnetic domains to determine the magnetization direction of the first magnetic domain.Type: GrantFiled: September 6, 2019Date of Patent: June 15, 2021Assignee: TOSHIBA MEMORY CORPORATIONInventors: Marie Takada, Masanobu Shirakawa, Yoshihiro Ueda, Naomi Takeda, Hideki Yamada
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Patent number: 11022512Abstract: A measurement system (20) includes pressure measurement apparatuses (220, 221, 222) capable of measuring pressure. The pressure measurement apparatuses (220, 221, 222) measure pressure at a measurement timing designated by a trigger signal.Type: GrantFiled: May 13, 2019Date of Patent: June 1, 2021Assignees: YOKOGAWA ELECTRIC CORPORATION, Yokogawa Test & Measurement CorporationInventors: Hirokazu Nagashima, Tadahiko Iinuma, Hironori Kurihara, Hideki Yamada
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Publication number: 20210089392Abstract: According to one embodiment, a memory system controls a shift resister memory and writes encoded data including a plurality of error correction code frames into a block of the shift resister memory. The memory system is configured to store, into a location corresponding to a first layer in a first data storing shift string, first data included in a first error correction code frame, to store, into a location corresponding to a second layer in the first data storing shift string, second data included in a second error correction code frame, and to store, into a location corresponding to the second layer in a second data storing shift string, third data included in the first error correction code frame.Type: ApplicationFiled: March 3, 2020Publication date: March 25, 2021Applicant: Kioxia CorporationInventors: Masanobu SHIRAKAWA, Hideki YAMADA, Marie TAKADA, Ryo YAMAKI, Osamu TORII, Naomi TAKEDA
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Patent number: 10957405Abstract: A memory system includes a semiconductor storage device including a memory cell array including a plurality of groups of memory cells, and a control circuit configured to perform, upon receipt of a write command, a write operation on one of the groups of memory cells, and a memory controller is configured to, when transmitting the write command to perform the write operation on the one of the groups of memory cells, determine a first write voltage value for the write operation based on a total number of write operations or erase operations that have been performed on the one of the groups of memory cells, and transmit the write command to the semiconductor storage device together with the determined first write voltage value.Type: GrantFiled: August 22, 2019Date of Patent: March 23, 2021Assignee: TOSHIBA MEMORY CORPORATIONInventors: Hideki Yamada, Masanobu Shirakawa
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Patent number: 10954959Abstract: A compressor includes: an upper half casing having upper half casing parting planes; upper half diaphragms configured to be disposed on an inner circumferential side of the upper half casing and having upper half diaphragm parting planes; and upper half position regulating parts that regulate positions of the upper half casing and the upper half diaphragms. The upper half position regulating parts are fixed to at least one of the upper half casing and one of the upper half diaphragms, and have upper half abutting members at which upper half abutting surfaces, each of which comes into contact with an upper half casing recessed surface of the upper half casing and an upper half diaphragm recessed surface of the upper half diaphragm, are formed.Type: GrantFiled: August 29, 2018Date of Patent: March 23, 2021Assignee: MITSUBISHI HEAVY INDUSTRIES COMPRESSOR CORPORATIONInventors: Hideki Yamada, Jun Koyanagi
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Publication number: 20210082510Abstract: In connection with a write operation, a memory controller transmits a first command sequence to a memory chip, thereby causing the memory chip to execute a first-stage program operation that includes a first operation and a first part of a second operation after the first operation, and a second command sequence to the memory chip after the first-stage program operation is executed, thereby causing the memory chip to execute a second-stage program operation that includes a second part of the second operation and no part of the first operation. During the first operation, a program voltage is applied a plurality of times while increasing the program voltage each of the times by a first step size. During the second operation, the program voltage is applied a plurality of times while increasing the program voltage each of the times by a second step size smaller than the first step size.Type: ApplicationFiled: February 26, 2020Publication date: March 18, 2021Inventors: Hideki YAMADA, Marie TAKADA, Masanobu SHIRAKAWA
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Patent number: 10837514Abstract: A valve structure of a shock absorber includes a piston to which a first communication passage and a second communication passage are provided, and a load application member that applies an initial load to a first leaf valve. The initial load is applied to the first leaf valve within a range between the inside in the radial direction from a first seat part and the outside in the radial direction from an abutting part of the piston, the first seat part being positioned on the outside in the radial direction of the first communication passage.Type: GrantFiled: August 2, 2016Date of Patent: November 17, 2020Assignee: KYB CORPORATIONInventors: Kazuyuki Kimishima, Hideki Yamada, Makoto Arano, Kenji Hibi, Koji Kawamura