Patents by Inventor Hideki Yamazaki

Hideki Yamazaki has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 5241440
    Abstract: A thin film magnetic head including conductor coils, a plurality of insulating layers to interpose and insulate the conductor coils and a magnetic gap layer between upper and lower magnetic cores, in which another insulating layer is provided on a stepped region formed by end faces of the plurality of insulating layers.
    Type: Grant
    Filed: June 29, 1992
    Date of Patent: August 31, 1993
    Assignee: Hitachi, Ltd.
    Inventors: Eizi Ashida, Moriaki Fuyama, Hideki Yamazaki, Shinji Narishige, Makoto Morijiri, Takashi Kawabe, Shunichiro Kuwatsuka, Saburo Suzuki, Eisei Togawa
  • Patent number: 5179635
    Abstract: An image memory controller having a first address signal generation means for generating a first address signal in response to a state signal representing the operational state of a printer. The first address signal corresponds to a location in an image memory. A second address signal generation means generates a second address signal for refreshing the image memory and a third address signal generation means generates a third address signal used for rewriting at least part of data stored in the image memory. An address signal selection means selectively delivers any of the first, second, and third address signals to the image memory.
    Type: Grant
    Filed: June 11, 1991
    Date of Patent: January 12, 1993
    Assignee: Hitachi, Ltd.
    Inventors: Hideki Yamazaki, Hiroshi Takeda, Yoshikazu Yokota
  • Patent number: 5129055
    Abstract: A display control system is provided which includes window management circuits having a plurality of area setting registers for individually setting a plurality of window display areas on a display surface, and for judging sequentially for each window whether or not a display position on the display surface is contained in the area designated by the register. A window display priority designation circuit is also provided having a plurality of priority setting registers for setting display priority of each window, and for determining which window has higher priority among a plurality of windows which are determined as containing the present display position on the basis of the content of the priority setting register and the result of a determination of which windows contain the present display position made by the window management circuit.
    Type: Grant
    Filed: March 18, 1991
    Date of Patent: July 7, 1992
    Assignee: Hitachi, Ltd.
    Inventors: Hideki Yamazaki, Hiroshi Takeda
  • Patent number: 5067097
    Abstract: An image memory controller having a first address signal generator for generating a first address signal in response to a state signal representing the operational state of a printer. The first address signal corresponds to a location in an image memory. A second address signal generator generates a second address signal for refreshing the image memory and a third address signal generation means generates a third address signal used for rewriting at least part of data stored in the image memory. An address signal selector selectively delivers any of the first, second and third address signals to the image memory.
    Type: Grant
    Filed: March 8, 1990
    Date of Patent: November 19, 1991
    Assignee: Hitachi, Ltd.
    Inventors: Hideki Yamazaki, Hiroshi Takeda, Yoshikazu Yokota