Patents by Inventor Hideki Yoshida

Hideki Yoshida has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8810717
    Abstract: The camera body includes an imaging element, a hot shoe, an internal light source, and a camera controller. The camera controller is configured to calculate an evaluation value on the basis of the image data produced by the imaging element, and perform video autofocusing on the basis of the evaluation value. When the camera controller decides that the auxiliary light is needed, and that the flash device mounted to the hot shoe has an external auxiliary light source arranged to emit near infrared light, the internal light source emits light during the video autofocusing.
    Type: Grant
    Filed: April 5, 2012
    Date of Patent: August 19, 2014
    Assignee: Panasonic Corporation
    Inventors: Kenichi Honjo, Hideki Yoshida, Keizo Ishiguro, Takayuki Hayashi
  • Patent number: 8775752
    Abstract: A virtual memory management apparatus of an embodiment is embedded in a computing machine 80 and is provided with an application program 21, an operating system 22, a volatile memory 11, and a nonvolatile memory 12. The volatile memory 11 is provided with a plurality of clean pages. The nonvolatile memory 12 is provided with a plurality of dirty pages and a page table memory unit 51. The operating system 22 is provided with a virtual memory management unit 23 which includes a page transfer unit 25.
    Type: Grant
    Filed: February 13, 2012
    Date of Patent: July 8, 2014
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Hideki Yoshida, Tatsunori Kanai, Masaya Tarui, Yutaka Yamada
  • Publication number: 20140186736
    Abstract: Provided is a solid oxide fuel cell module that is small in size and is capable of stably generating power. A plurality of power generation units and are located such that a first fuel cell and an oxidant gas preheater connected to a second fuel cell adjacent to the first fuel cell are adjacent to each other. A solid oxide fuel cell module includes a partition member. The partition member partitions a combustion chamber into a region including the first fuel cell and a region including the second fuel cell as well as into the region including the first fuel cell and a region including the oxidant gas preheater connected to the second fuel cell.
    Type: Application
    Filed: December 2, 2013
    Publication date: July 3, 2014
    Applicants: Tokyo Gas Co., Ltd. (Corporation of Japan), MURATA MANUFACTURING CO., LTD.
    Inventors: Yosuke Tomoshige, Kimihiro Mizukami, Masato Inaoka, Hideki Yoshida, Kei Ogasawara, Shinji Amaha
  • Publication number: 20140157157
    Abstract: An information processing apparatus includes a display, a touch panel provided on the display, a storage, a connection detector, and a controller. The storage stores plural kinds of software key arrangement information. The connection detector detects whether or not an input device in which mechanical keys are arranged is connected, and outputs a connection detection result. The controller determines arrangement information to be used among the plural kinds of software key arrangement information according to the connection detection result which is output from the connection detector, and causes the display to display software keys based on the determined arrangement information.
    Type: Application
    Filed: June 10, 2013
    Publication date: June 5, 2014
    Inventor: Hideki Yoshida
  • Publication number: 20140152592
    Abstract: An information processing apparatus includes a screen on which software keys are displayed, a touch detector, a key detector, a key input time acquiring module, and a touch input restricting module. The touch detector detects a touch manipulation of a software key. The key detector detects a key manipulation on an input device in which mechanical keys are arranged. The key input time acquiring module acquires a detection time of the key manipulation, and stores the acquired time in a memory. The touch input restricting module acquires a detection time of the touch manipulation, reads the detection time of the key manipulation from the memory, and restricts acceptance of the touch manipulation according to whether or not a time from the detection time of the key manipulation to the detection time of the touch manipulation is longer than or equal to a first prescribed time.
    Type: Application
    Filed: September 24, 2013
    Publication date: June 5, 2014
    Applicant: Kabushiki Kaisha Toshiba
    Inventor: Hideki Yoshida
  • Patent number: 8683249
    Abstract: According to one embodiment, a computer system comprises a first memory that stores a first program, a second memory that stores a second program or data, a processor, a first and a second power control circuits. The first power control circuit causes the first memory to operate at a first power consumption when detecting change of an input signal to the processor, and causes the first memory to operate at a second power consumption smaller than the first power consumption and transmits a temporary halt instruction to the processor when the execution of the first program or the second program by the processor is completed. The second power control circuit causes the second memory to operate at a third power consumption before the processor executes the second program, reads or writes the data. The second memory accepts read and write operations while operating at the third power consumption.
    Type: Grant
    Filed: December 5, 2011
    Date of Patent: March 25, 2014
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Tatsunori Kanai, Yutaka Yamada, Hideki Yoshida, Masaya Tarui
  • Patent number: 8453002
    Abstract: According to one embodiment, an electronic apparatus includes a first power saver, a second power saver and a controller. The first power saver executes switching from an operable condition to a first power saving state. The second power saver executes switching from the first state to a second state in which power consumption is smaller than that in the first state. The controller determines whether timer event processing executable in the first state is scheduled within a predetermined period of time when the switching from the operable condition to the second state is required, and controls the first power saver and the second power saver so as to execute switching to the first state and maintains the first state without switching to the second state, when the timer event processing is scheduled within the predetermined period of time.
    Type: Grant
    Filed: August 26, 2011
    Date of Patent: May 28, 2013
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Hideki Yoshida
  • Patent number: 8405034
    Abstract: A neutron measurement apparatus 1A includes a neutron detection unit 10, a photodetection unit 20 that detects scintillation light emitted from the neutron detection unit 10, a light guide optical system 15 that guides the scintillation light from the neutron detection unit 10 to the photodetection unit 20, and a shielding member 30 which is located between the neutron detection unit 10 and the photodetection unit 20 for shielding radiation passing in a direction toward the photodetection unit 20. Further, a scintillator formed of a lithium glass material in which PrF3 is doped to a glass material 20Al(PO3)3-80LiF is used as a neutron detection scintillator composing the neutron detection unit 10. Thereby, the neutron detection scintillator and the neutron measurement apparatus which are capable of suitably performing neutron measurement such as measurement of scattered neutrons from an implosion plasma can be realized.
    Type: Grant
    Filed: April 27, 2010
    Date of Patent: March 26, 2013
    Assignees: Osaka University, TOKAI UNIVERSITY Educational System
    Inventors: Hiroshi Azechi, Nobuhiko Sarukura, Yasunobu Arikawa, Mitsuo Nakai, Hirofumi Kan, Takahiro Murata, Toshihisa Suyama, Shigeru Fujino, Yoshiyuki Usuki, Hideki Yoshida, Akira Yoshikawa
  • Publication number: 20120249597
    Abstract: A display control apparatus includes a display module, a virtual desktop module, a determining module, and a control module. The display module displays a first image having a first size. The virtual desktop module sets, as the first image to be displayed by the display module, a partial region of a second image having a second size that is larger than the first size. The determining module allows a user to determine a region of the second image to be set as the first image by the virtual desktop module. The control module controls the virtual desktop module to change the determined region so that an undisplayed part of an object that exists in the determined region is displayed or the whole of the object is undisplayed where the object has the undisplayed part.
    Type: Application
    Filed: December 12, 2011
    Publication date: October 4, 2012
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventor: Hideki YOSHIDA
  • Publication number: 20120200765
    Abstract: The camera body includes an imaging element, a hot shoe, an internal light source, and a camera controller. The camera controller is configured to calculate an evaluation value on the basis of the image data produced by the imaging element, and perform video autofocusing on the basis of the evaluation value. When the camera controller decides that the auxiliary light is needed, and that the flash device mounted to the hot shoe has an external auxiliary light source arranged to emit near infrared light, the internal light source emits light during the video autofocusing.
    Type: Application
    Filed: April 5, 2012
    Publication date: August 9, 2012
    Applicant: PANASONIC CORPORATION
    Inventors: KENICHI HONJO, HIDEKI YOSHIDA, KEIZO ISHIGURO, TAKAYUKI HAYASHI
  • Patent number: 8218069
    Abstract: The camera body includes an imaging element, a hot shoe, an internal light source, and a camera controller. The imaging element is configured to convert an optical image of the subject into an electrical signal, and is configured to produce image data for the subject. The hot shoe allows the flash device to be mounted. The internal light source is arranged to shine light on the subject. The camera controller is configured to calculate an evaluation value on the basis of the image data produced by the imaging element, and is configured to perform video autofocusing on the basis of the evaluation value.
    Type: Grant
    Filed: September 17, 2009
    Date of Patent: July 10, 2012
    Assignee: Panasonic Corporation
    Inventors: Kenichi Honjo, Hideki Yoshida, Keizo Ishiguro, Takayuki Hayashi
  • Publication number: 20120151119
    Abstract: A virtual memory management apparatus of an embodiment is embedded in a computing machine 80 and is provided with an application program 21, an operating system 22, a volatile memory 11, and a nonvolatile memory 12. The volatile memory 11 is provided with a plurality of clean pages. The nonvolatile memory 12 is provided with a plurality of dirty pages and a page table memory unit 51. The operating system 22 is provided with a virtual memory management unit 23 which includes a page transfer unit 25.
    Type: Application
    Filed: February 13, 2012
    Publication date: June 14, 2012
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Hideki Yoshida, Tatsunori Kanai, Masaya Tarui, Yutaka Yamada
  • Publication number: 20120137155
    Abstract: According to one embodiment, an electronic apparatus includes a first power saver, a second power saver and a controller. The first power saver executes switching from an operable condition to a first power saving state. The second power saver executes switching from the first state to a second state in which power consumption is smaller than that in the first state. The controller determines whether timer event processing executable in the first state is scheduled within a predetermined period of time when the switching from the operable condition to the second state is required, and controls the first power saver and the second power saver so as to execute switching to the first state and maintains the first state without switching to the second state, when the timer event processing is scheduled within the predetermined period of time.
    Type: Application
    Filed: August 26, 2011
    Publication date: May 31, 2012
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventor: Hideki YOSHIDA
  • Patent number: 8190759
    Abstract: The present invention provides a transmission/reception apparatus capable of achieving both a high processing speed and good extensibility in performing communication protocol processes. Used for transmitting data in accordance with a predetermined communication protocol and receiving data transmitted in accordance with the predetermined communication protocol, the transmission/reception apparatus has a configuration capable of executing communication protocol processes by using hardware (in first and second communication-protocol-processing units) and software (in first and second control units). The hardware or the software can be selected properly in accordance with the type of data. For example, a communication protocol process for data regarded as a heavy processing load can be carried out by using the hardware at the high processing speed whereas a communication protocol process for data regarded as a light processing load can be carried out by using the software, which offers the good extensibility.
    Type: Grant
    Filed: September 20, 2010
    Date of Patent: May 29, 2012
    Assignee: Sony Corporation
    Inventors: Satoru Maeda, Hideki Yoshida, Manabu Onishi, Kei Yamashita, Kazuyuki Ikeda, Daisuke Kawaguchi, Munehiro Yoshikawa
  • Publication number: 20120131418
    Abstract: According to one embodiment, a memory device comprises a writing device that writes data bits, check bits for error corrections, and overhead bit(s) into a memory, each bit of the overhead bit(s) corresponding to each group of bit group(s) including at least one bit of the data bits and/or the check bits, each bit of the overhead bit(s) indicating whether the corresponding bit group has been inverted, a reading unit that reads the data bits, the check bits, and the overhead bit(s) from the memory, a correcting unit that corrects an error in the data bits and overhead bit(s) read from the memory, based on the check bits, and an inverting unit that inverts the data bits contained in the bit group corresponding to the overhead bit and outputs the inverted data bits as data read from the memory when the error-corrected overhead bit indicates that inversion has been performed.
    Type: Application
    Filed: January 30, 2012
    Publication date: May 24, 2012
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Masaya Tarui, Tatsunori Kanai, Yutaka Yamada, Hideki Yoshida
  • Publication number: 20120117407
    Abstract: According to one embodiment, a computer system comprises a first memory that stores a first program, a second memory that stores a second program or data, a processor, a first and a second power control circuits. The first power control circuit causes the first memory to operate at a first power consumption when detecting change of an input signal to the processor, and causes the first memory to operate at a second power consumption smaller than the first power consumption and transmits a temporary halt instruction to the processor when the execution of the first program or the second program by the processor is completed. The second power control circuit causes the second memory to operate at a third power consumption before the processor executes the second program, reads or writes the data. The second memory accepts read and write operations while operating at the third power consumption.
    Type: Application
    Filed: December 5, 2011
    Publication date: May 10, 2012
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Tatsunori Kanai, Yutaka Yamada, Hideki Yoshida, Masaya Tarui
  • Publication number: 20120091351
    Abstract: A neutron measurement apparatus 1A includes a neutron detection unit 10, a photodetection unit 20 that detects scintillation light emitted from the neutron detection unit 10, a light guide optical system 15 that guides the scintillation light from the neutron detection unit 10 to the photodetection unit 20, and a shielding member 30 which is located between the neutron detection unit 10 and the photodetection unit 20 for shielding radiation passing in a direction toward the photodetection unit 20. Further, a scintillator formed of a lithium glass material in which PrF3 is doped to a glass material 20Al(PO3)3-80LiF is used as a neutron detection scintillator composing the neutron detection unit 10. Thereby, the neutron detection scintillator and the neutron measurement apparatus which are capable of suitably performing neutron measurement such as measurement of scattered neutrons from an implosion plasma can be realized.
    Type: Application
    Filed: April 27, 2010
    Publication date: April 19, 2012
    Applicants: OSAKA UNIVERSITY, TOKAI UNIVERSITY EDUCATIONAL SYSTEM, HAMAMATSU PHOTONICS K.K., FURUKAWA CO., LTD, NAGASAKI PREFECTURAL GOVERNMENT, TOKUYAMA CORPORATION
    Inventors: Hiroshi Azechi, Nobuhiko Sarukura, Yasunobu Arikawa, Mitsuo Nakai, Hirofumi Kan, Takahiro Murata, Toshihisa Suyama, Shigeru Fujino, Yoshiyuki Usuki, Hideki Yoshida, Akira Yoshikawa
  • Publication number: 20110297424
    Abstract: A wiring board which uses both conductor patterns and reflection members provided at gaps therebetween to suppress unevenness in the reflection rate so as to raise the overall reflection rate and provide a reflection function on the surface of the wiring board at the side where an electronic device is mounted; facilitates shaping of the reflection members, controlling of the thickness of the reflection members, and controlling of the surface shape of the reflection members so as to stabilize the reflection rate; and secures close contact between the reflection members and sealing members so as to improve reliability. The wiring board comprises a plurality of wiring layers provided with conductor patterns disposed on base members, and base members which electrically insulate the plurality of wiring layers.
    Type: Application
    Filed: February 22, 2010
    Publication date: December 8, 2011
    Inventors: Hideki Yoshida, Satoshi Isoda, Naoyuki Urasaki, Hayato Kotani
  • Patent number: 7933949
    Abstract: A data processing apparatus constitutes a low-cost audio/video data transmission and reception system. A reception buffer monitoring circuit 21 monitors the size of receiver data being accumulated in a reception buffer 6. When the size of accumulated data is found to become higher than a high threshold, the circuit 21 causes a reception clock generation circuit 8 to generate a reception clock with a higher frequency. When the accumulated data size becomes lower than a low threshold, the reception clock is generated with a lower frequency. Based on the reception clock fed from the reception clock generation circuit 8, an audio/video decoder 7 decodes the audio/video data coming from the reception buffer 6. The data processing apparatus applies advantageously to a television transmission and reception system for transmitting and receiving TV broadcast signals.
    Type: Grant
    Filed: May 1, 2008
    Date of Patent: April 26, 2011
    Assignee: Sony Corporation
    Inventors: Hideki Yoshida, Jin Sato, Kazuyuki Ikeda, Takashi Norizuki, Kenichi Sakusabe, Daisuke Kawaguchi, Munehiro Yoshikawa
  • Publication number: 20110007826
    Abstract: The present invention provides a transmission/reception apparatus capable of achieving both a high processing speed and good extensibility in performing communication protocol processes. Used for transmitting data in accordance with a predetermined communication protocol and receiving data transmitted in accordance with the predetermined communication protocol, the transmission/reception apparatus has a configuration capable of executing communication protocol processes by using hardware (in first and second communication-protocol-processing units) and software (in first and second control units). The hardware or the software can be selected properly in accordance with the type of data. For example, a communication protocol process for data regarded as a heavy processing load can be carried out by using the hardware at the high processing speed whereas a communication protocol process for data regarded as a light processing load can be carried out by using the software, which offers the good extensibility.
    Type: Application
    Filed: September 20, 2010
    Publication date: January 13, 2011
    Inventors: Satoru MAEDA, Hideki YOSHIDA, Manabu ONISHI, Kei YAMASHITA, Kazayuki IKEDA, Daisuke KAWAGUCHI, Munehiro YOSHIKAWA