Patents by Inventor Hideki Yoshida

Hideki Yoshida has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20200363996
    Abstract: According to one embodiment, a memory system receives, from a host, a write request including a first identifier associated with one write destination block and storage location information indicating a location in a write buffer on a memory of the host in which first data to be written is stored. When the first data is to be written to a nonvolatile memory, the memory system obtains the first data from the write buffer by transmitting a transfer request including the storage location information to the host, transfers the first data to the nonvolatile memory, and writes the first data to the one write destination block.
    Type: Application
    Filed: August 4, 2020
    Publication date: November 19, 2020
    Inventors: Shinichi Kanno, Hideki Yoshida
  • Patent number: 10824217
    Abstract: According to one embodiment, a storage includes a nonvolatile memory and a controller configured to control the nonvolatile memory. The storage is supplied with first power from a power supply unit. The controller is configured to change power supplied from the power supply unit from the first power to second power based on a power control command transmitted from a host. The power control command includes a first parameter identifying the storage and a second parameter indicative of the second power.
    Type: Grant
    Filed: December 20, 2018
    Date of Patent: November 3, 2020
    Assignee: Toshiba Memory Corporation
    Inventors: Naoki Sawai, Hiroshi Murayama, Hiroshi Nishimura, Shinichi Kanno, Hideki Yoshida
  • Publication number: 20200341681
    Abstract: According to one embodiment, a memory system includes a nonvolatile memory and a controller. The controller acquires, from a host, write data having the same first size as a data write unit of the nonvolatile memory and obtained by dividing write data associated with one write command having a first identifier indicating a first write destination block in a plurality of write destination blocks into a plurality of write data or combining write data associated with two or more write commands having the first identifier. The controller writes the acquired write data having the first size to the first write destination block by a first write operation.
    Type: Application
    Filed: July 14, 2020
    Publication date: October 29, 2020
    Applicant: TOSHIBA MEMORY CORPORATION
    Inventors: Shinichi KANNO, Hideki Yoshida, Naoki Esaka, Hiroshi Nishimura
  • Patent number: 10808453
    Abstract: The objective is to propose a production method of multiple panes which can be simple and nevertheless produce a multiple pane in its finished state which does not include any undesired protrusion from an external surface of a glass panel. The production method includes: hermetically bonding, with a sealing member, peripheries of paired glass panels disposed facing each other at a predetermined distance to form a space to be hermetically enclosed between the glass panels; evacuating air from the space through an outlet to make the space be in a reduced pressure state; subsequently dividing the space by a region forming member disposed inside the space to form a partial region which do not include the outlet; and subsequently cutting out the partial regions by cutting the pair of glass panels.
    Type: Grant
    Filed: February 22, 2018
    Date of Patent: October 20, 2020
    Assignee: PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO., LTD.
    Inventors: Hiroyuki Abe, Masataka Nonaka, Hideki Yoshida, Eiichi Uriu, Kenji Hasegawa
  • Publication number: 20200310961
    Abstract: According to one embodiment, a memory system includes a nonvolatile memory including plural blocks each including plural pages, and a controller. When receiving a write request designating a first logical address and a first block number from the host, the controller determines a first location in a first block having the first block number to which data from the host should be written, and writes the data from the host to the first location in the first block. The controller notifies the host of either an in-block physical address indicative of the first location, or a group of the first logical address, the first block number and the first in-block physical address.
    Type: Application
    Filed: June 12, 2020
    Publication date: October 1, 2020
    Inventors: Hideki Yoshida, Shinichi Kanno
  • Publication number: 20200307998
    Abstract: A method of manufacturing hexagonal boron nitride fibers includes: providing amorphous fibrous boron nitride; performing heat treatment on the amorphous fibrous boron nitride at a first temperature of 500° C. or greater and less than 900° C. in an oxygen-containing atmosphere to obtain a first heat-treated product; and performing heat treatment on the first heat-treated product at a second temperature in a range of 1000° C. to 1800° C. in a nitrogen-containing atmosphere to obtain a second heat-treated product containing hexagonal boron nitride.
    Type: Application
    Filed: March 25, 2020
    Publication date: October 1, 2020
    Applicant: NICHIA CORPORATION
    Inventor: Hideki YOSHIDA
  • Patent number: 10789167
    Abstract: According to one embodiment, an information processing apparatus stores first data to be written to one destination block of a nonvolatile memory in a write buffer on a memory of the information processing apparatus. The information processing apparatus transmits, to a storage device, a write request including a first identifier associated with the one write destination block and storage location information indicating a location in the write buffer in which the first data is stored. The information processing apparatus transfers the first data from the write buffer to the storage device every time a transfer request including the storage location information is received from the storage device.
    Type: Grant
    Filed: June 11, 2018
    Date of Patent: September 29, 2020
    Assignee: Toshiba Memory Corporation
    Inventors: Shinichi Kanno, Hideki Yoshida
  • Patent number: 10768858
    Abstract: According to one embodiment, a memory system receives, from a host, a write request including a first identifier associated with one write destination block and storage location information indicating a location in a write buffer on a memory of the host in which first data to be written is stored. When the first data is to be written to a nonvolatile memory, the memory system obtains the first data from the write buffer by transmitting a transfer request including the storage location information to the host, transfers the first data to the nonvolatile memory, and writes the first data to the one write destination block.
    Type: Grant
    Filed: June 11, 2018
    Date of Patent: September 8, 2020
    Assignee: Toshiba Memory Corporation
    Inventors: Shinichi Kanno, Hideki Yoshida
  • Patent number: 10761771
    Abstract: According to one embodiment, a memory system includes a nonvolatile memory and a controller. The controller acquires, from a host, write data having the same first size as a data write unit of the nonvolatile memory and obtained by dividing write data associated with one write command having a first identifier indicating a first write destination block in a plurality of write destination blocks into a plurality of write data or combining write data associated with two or more write commands having the first identifier. The controller writes the acquired write data having the first size to the first write destination block by a first write operation.
    Type: Grant
    Filed: March 13, 2019
    Date of Patent: September 1, 2020
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventors: Shinichi Kanno, Hideki Yoshida, Naoki Esaka, Hiroshi Nishimura
  • Patent number: 10751732
    Abstract: There can be provided a bucket for a swinging rotor of a centrifugal separator that can be readily carried while ensuring the sealability at the time of a centrifugal treatment or the carriage operation. The bucket includes a bucket body (11) in a bottomed cylindrical shape, a cover main body (21) (cover), a packing (22) (seal member), and a pair of attachment mechanisms (34) configured to detachably attach the cover main body (21) to the bucket body (11). The cover main body (21) includes a lid portion (24) having clip fixing portions (31) (pressed portions) and configured to cover an opening (11a) of the bucket body (11), and a handle portion (25) formed integrally with the lid portion (24). The handle portion (25) is stretched between the pair of clip fixing portions (31). A handle concave portion (36) (hole) that opens toward the outside of the cover main body (21) and separates the lid portion (24) and the handle portion (25) is formed between the lid portion (24) and the handle portion (25).
    Type: Grant
    Filed: June 15, 2016
    Date of Patent: August 25, 2020
    Assignee: KUBOTA MANUFACTURING CORPORATION
    Inventor: Hideki Yoshida
  • Patent number: 10719437
    Abstract: According to one embodiment, a memory system includes a nonvolatile memory including plural blocks each including plural pages, and a controller. When receiving a write request designating a first logical address and a first block number from the host, the controller determines a first location in a first block having the first block number to which data from the host should be written, and writes the data from the host to the first location in the first block. The controller notifies the host of either an in-block physical address indicative of the first location, or a group of the first logical address, the first block number and the first in-block physical address.
    Type: Grant
    Filed: May 21, 2018
    Date of Patent: July 21, 2020
    Assignee: Toshiba Memory Corporation
    Inventors: Hideki Yoshida, Shinichi Kanno
  • Publication number: 20200192600
    Abstract: According to one embodiment, a memory system receives from a host a first write request including a first block identifier designating a first write destination block to which first write data is to be written. The memory system acquires the first write data from a write buffer temporarily holding write data corresponding to each of the write requests, and writes the first write data to a write destination page in the first write destination block. The memory system releases a region in the write buffer, storing data which is made readable from the first write destination block by writing the first write data to the write destination page. The data made readable is a data of a page in the first write destination block preceding the write destination page.
    Type: Application
    Filed: February 27, 2020
    Publication date: June 18, 2020
    Applicant: Toshiba Memory Corporation
    Inventors: Shinichi Kanno, Hideki Yoshida, Naoki Esaka
  • Publication number: 20200133879
    Abstract: According to one embodiment, when a read request received from a host includes a first identifier indicative of a first region, a memory system obtains a logical address from the received read request, obtains a physical address corresponding to the obtained logical address from a logical-to-physical address translation table which manages mapping between logical addresses and physical addresses of the first region, and reads data from the first region, based on the obtained physical address. When the received read request includes a second identifier indicative of a second region, the memory system obtains physical address information from the read request, and reads data from the second region, based on the obtained physical address information.
    Type: Application
    Filed: December 23, 2019
    Publication date: April 30, 2020
    Inventors: Hideki Yoshida, Shinichi Kanno
  • Publication number: 20200122320
    Abstract: Examples of a method for teaching a transportation position includes correcting the position of an alignment jig having a plurality of sloping surfaces relative to a susceptor pin projecting upwards from an upper surface of a susceptor by lowering a robot hand to bring one of the sloping surfaces into contact with the susceptor pin and causing the susceptor pin to slide on the sloping surfaces by virtue of an own weight of the aliment jig, detecting a position of the alignment jig before and after the positional correction of the alignment jig, and correcting a movement destination information by an amount corresponding to a difference between an initial position and a corrected position of the alignment jig.
    Type: Application
    Filed: October 19, 2018
    Publication date: April 23, 2020
    Applicant: ASM IP Holding B.V.
    Inventors: Hideki YOSHIDA, Masaei SUWADA
  • Publication number: 20200125487
    Abstract: According to one embodiment, a memory system determine both of a first block to which data from a host is to be written and a first location of the first block, when receiving a write request to designate a first logical address from the host. The memory system writes the data from the host to the first location of the first block. The memory system notifies the host of the first logical address, a first block number designating the first block, and a first in-block offset indicating an offset from a leading part of the first block to the first location by a multiple of grain having a size different from a page size.
    Type: Application
    Filed: December 20, 2019
    Publication date: April 23, 2020
    Inventors: Shinichi Kanno, Hideki Yoshida
  • Patent number: 10613796
    Abstract: According to one embodiment, a memory system receives from a host a first write request including a first block identifier designating a first write destination block to which first write data is to be written. The memory system acquires the first write data from a write buffer temporarily holding write data corresponding to each of the write requests, and writes the first write data to a write destination page in the first write destination block. The memory system releases a region in the write buffer, storing data which is made readable from the first write destination block by writing the first write data to the write destination page. The data made readable is a data of a page in the first write destination block preceding the write destination page.
    Type: Grant
    Filed: September 10, 2018
    Date of Patent: April 7, 2020
    Assignee: Toshiba Memory Corporation
    Inventors: Shinichi Kanno, Hideki Yoshida, Naoki Esaka
  • Publication number: 20200057559
    Abstract: According to one embodiment, when receiving a write request to designate a first block number and a first logical address from a host, a memory system determines a first location in a first block having the first block number, to which data from the host is to be written, and writes the data from the host to the first location of the first block. The memory system updates a first address translation table managing mapping between logical addresses and in-block physical addresses of the first block, and maps a first in-block physical address indicative of the first location to the first logical address.
    Type: Application
    Filed: October 23, 2019
    Publication date: February 20, 2020
    Inventors: Hideki Yoshida, Shinichi Kanno
  • Publication number: 20200052296
    Abstract: A method of producing a nickel-cobalt composite hydroxide includes: preparing a first solution containing nickel ions and cobalt ions; preparing a second solution containing tungsten ions and having a pH of 10 or more; preparing a third solution containing a complex ion-forming factor; preparing a liquid medium having a pH in a range of 10 to 13.5; supplying the first solution, the second solution, and the third solution separately and simultaneously to the liquid medium to obtain a reacted solution having a pH in a range of 10 to 13.5; and obtaining the nickel-cobalt composite hydroxide containing nickel, cobalt, and tungsten from the reacted solution.
    Type: Application
    Filed: October 9, 2019
    Publication date: February 13, 2020
    Applicant: NICHIA CORPORATION
    Inventors: Hideki YOSHIDA, Masato SONOO, Takahiro KITAGAWA
  • Patent number: 10552336
    Abstract: According to one embodiment, when a read request received from a host includes a first identifier indicative of a first region, a memory system obtains a logical address from the received read request, obtains a physical address corresponding to the obtained logical address from a logical-to-physical address translation table which manages mapping between logical addresses and physical addresses of the first region, and reads data from the first region, based on the obtained physical address. When the received read request includes a second identifier indicative of a second region, the memory system obtains physical address information from the read request, and reads data from the second region, based on the obtained physical address information.
    Type: Grant
    Filed: May 21, 2018
    Date of Patent: February 4, 2020
    Assignee: Toshiba Memory Corporation
    Inventors: Hideki Yoshida, Shinichi Kanno
  • Patent number: 10545862
    Abstract: According to one embodiment, a memory system determine both of a first block to which data from a host is to be written and a first location of the first block, when receiving a write request to designate a first logical address from the host. The memory system writes the data from the host to the first location of the first block. The memory system notifies the host of the first logical address, a first block number designating the first block, and a first in-block offset indicating an offset from a leading part of the first block to the first location by a multiple of grain having a size different from a page size.
    Type: Grant
    Filed: March 7, 2018
    Date of Patent: January 28, 2020
    Assignee: Toshiba Memory Corporation
    Inventors: Shinichi Kanno, Hideki Yoshida