Patents by Inventor Hidemichi Furihata

Hidemichi Furihata has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7404885
    Abstract: A plating method includes the steps of (a) forming a roughened area in a predetermined area of a substrate, (b) forming a surface-active agent layer above at least the roughened area, (c) forming, above the roughened area, a catalyst layer above the surface-active agent layer, and (d) precipitating a metal layer above the catalyst layer.
    Type: Grant
    Filed: March 8, 2006
    Date of Patent: July 29, 2008
    Assignee: Seiko Epson Corporation
    Inventors: Hidemichi Furihata, Satoshi Kimura
  • Publication number: 20080173471
    Abstract: An element substrate including a substrate and a metal layer formed on the substrate by electroless plating and including a linear portion having a width of 10 nm to 100 nm.
    Type: Application
    Filed: January 16, 2008
    Publication date: July 24, 2008
    Inventors: Toshihiko Kaneda, Satoshi Kimura, Hidemichi Furihata, Jun Amako, Daisuke Sawaki, Takeshi Kijima
  • Patent number: 7361594
    Abstract: Aspects of the invention can provide a method of manufacturing a thin film transistor capable of manufacturing a high-performance thin film transistor with a simple process, a thin film transistor manufactured using the method of manufacturing a thin film transistor, and a thin film transistor circuit, an electronic device, and an electronic apparatus each equipped with the thin film transistor.
    Type: Grant
    Filed: November 16, 2004
    Date of Patent: April 22, 2008
    Assignee: Seiko Epson Corporation
    Inventors: Takeo Kawase, Mitsuaki Harada, Satoshi Kimura, Hidemichi Furihata
  • Publication number: 20080081155
    Abstract: A method of manufacturing a plated substrate using electroless plating to form a metal layer, the method including: forming a resin section having a predetermined pattern on a substrate; forming a catalyst layer on the resin section; and depositing a metal on the catalyst layer by immersing the substrate in an electroless plating solution to form a metal layer.
    Type: Application
    Filed: October 2, 2007
    Publication date: April 3, 2008
    Inventors: Toshihiko Kaneda, Satoshi Kimura, Hidemichi Furihata, Jun Amako, Daisuke Sawaki, Takeshi Kijima
  • Publication number: 20080081154
    Abstract: A method of manufacturing an element substrate including: forming a release layer on a first support substrate; forming a metal layer having a predetermined pattern on the release layer; disposing a second support substrate on the first support substrate so that the metal layer is interposed between the first and second support substrates; pouring a resin material in a fluid state between the first and second support substrates; curing the resin material to form a resin substrate; and removing the metal layer from the first support substrate by decomposing the release layer to transfer the metal layer to the resin substrate.
    Type: Application
    Filed: October 2, 2007
    Publication date: April 3, 2008
    Inventors: Toshihiko Kaneda, Satoshi Kimura, Hidemichi Furihata, Takeshi Kijima
  • Publication number: 20080003161
    Abstract: A method of manufacturing a complex metal oxide powder, the method including: preparing a raw material composition for forming a complex metal oxide; mixing an oxidizing solution including an oxidizing substance into the raw material composition to produce complex metal oxide particles to obtain a liquid dispersion of the particles; and separating the particles from the liquid dispersion to obtain a complex metal oxide powder. The complex metal oxide is shown by a general formula AB1-xCxO3, an element A including at least Pb, an element B including at least one of Zr, Ti, V, W, and Hf, and an element C including at least one of Nb and Ta.
    Type: Application
    Filed: June 26, 2007
    Publication date: January 3, 2008
    Inventors: Takeshi Kijima, Hidemichi Furihata, Setsuya Iwashita, Satoshi Kimura, Toshihiko Kaneda
  • Patent number: 7305761
    Abstract: A method for manufacturing a wiring substrate includes the steps of: (a) forming a ground layer precursor having reactive groups including nitrogen atoms in first and second areas of a substrate; (b) irradiating light energy to remove the reactive groups from the ground layer precursor to thereby form a ground layer charged in cathode; (c) patterning a cationic surface-active agent of anode to be left on the first area of the substrate with the ground layer as a ground; (d) providing a catalyst at the surface-active agent; and (e) forming a wiring along the first area of the substrate by precipitating a metal layer to the catalyst.
    Type: Grant
    Filed: March 28, 2005
    Date of Patent: December 11, 2007
    Assignee: Seiko Epson Corporation
    Inventors: Satoshi Kimura, Hidemichi Furihata
  • Publication number: 20070218191
    Abstract: A method for manufacturing a wiring substrate by an electroless plating method that precipitates metal without using a plating resist is provided. The method includes the steps of: (a) providing a catalyst layer having a predetermined pattern on a substrate; (b) dipping the substrate in an electroless plating solution to thereby precipitate metal on the catalyst layer to provide a first metal layer; (c) exposing a top surface of the substrate to steam; and (d) dipping the substrate in an electroless plating solution to thereby precipitate metal on the first metal layer to provide a second metal layer.
    Type: Application
    Filed: March 1, 2007
    Publication date: September 20, 2007
    Applicant: SEIKO EPSON CORPORATION
    Inventors: Hidemichi FURIHATA, Satoshi KIMURA, Toshihiko KANEDA, Takeshi KIJIMA
  • Publication number: 20070218193
    Abstract: A method of manufacturing an interconnect substrate by electroless plating which causes a metal to be deposited without using a plating resist, the method including: (a) immersing a substrate in a catalyst solution including palladium, hydrogen peroxide, and hydrochloric acid to form a catalyst layer on the substrate; and (b) depositing a metal on the catalyst layer by immersing the substrate in an electroless plating solution to form a metal layer.
    Type: Application
    Filed: March 9, 2007
    Publication date: September 20, 2007
    Inventors: Satoshi Kimura, Hidemichi Furihata
  • Publication number: 20070218192
    Abstract: A method of manufacturing an interconnect substrate having a linear interconnect by electroless plating without using a plating resist, the method including: (a) forming a plurality of rows of linear catalyst layers on a substrate; and (b) depositing a metal on the linear catalyst layers by electroless plating to form a plurality of rows of linear metal layers, at least one of the rows of linear catalyst layers having a line width of 2 micrometers or less, and a total line width of the linear catalyst layers on the substrate being 10 micrometers or more.
    Type: Application
    Filed: March 9, 2007
    Publication date: September 20, 2007
    Inventors: Satoshi Kimura, Hidemichi Furihata, Toshihiko Kaneda
  • Publication number: 20070212876
    Abstract: A method for manufacturing a wiring substrate by an electroless plating method that precipitates metal without using a plating resist is provided. The method includes the steps of (a) providing a catalyst layer having a predetermined pattern on a substrate; (b) dipping the substrate in an electroless plating solution to thereby precipitate metal on the catalyst layer to provide a first metal layer; (c) washing a top surface of the substrate with water; and (d) dipping the substrate in an electroless plating solution to thereby precipitate metal on the first metal layer to provide a second metal layer.
    Type: Application
    Filed: March 1, 2007
    Publication date: September 13, 2007
    Applicant: SEIKO EPSON CORPORATION
    Inventors: Satoshi KIMURA, Hidemichi FURIHATA, Takeshi KIJIMA
  • Publication number: 20070212871
    Abstract: A method of manufacturing an interconnect substrate by electroless plating, including: (a) forming a catalyst layer with a specific pattern on a substrate; (b) immersing the substrate in a first electroless plating solution including a first metal to deposit the first metal on the catalyst layer to form a first metal layer; and (c) immersing the substrate in a second electroless plating solution including a second metal to deposit the second metal on the first metal layer to form a second metal layer, an ionization tendency of the first metal being higher than an ionization tendency of the second metal.
    Type: Application
    Filed: March 9, 2007
    Publication date: September 13, 2007
    Inventors: Satoshi Kimura, Hidemichi Furihata, Toshihiko Kaneda
  • Publication number: 20060231408
    Abstract: A plating method includes the steps of (a) forming a roughened area in a predetermined area of a substrate, (b) forming a surface-active agent layer above at least the roughened area, (c) forming, above the roughened area, a catalyst layer above the surface-active agent layer, and (d) precipitating a metal layer above the catalyst layer.
    Type: Application
    Filed: March 8, 2006
    Publication date: October 19, 2006
    Inventors: Hidemichi Furihata, Satoshi Kimura
  • Publication number: 20050245004
    Abstract: A method for manufacturing a wiring substrate includes the steps of (a) providing a surface-active agent in first and second areas of a substrate, (b) irradiating a vacuum ultraviolet radiation to the second area of the substrate to thereby break down an interatomic bond in the second area of the substrate, (c) washing the substrate to thereby remove a portion of the surface-active agent in the second area, (d) providing a catalyst on an area of the surface-active agent remaining in the first area, and (e) depositing a metal layer to the catalyst to thereby form a wiring composed of the metal layer along the first area.
    Type: Application
    Filed: February 3, 2005
    Publication date: November 3, 2005
    Inventors: Satoshi Kimura, Hidemichi Furihata, Minoru Marumo
  • Publication number: 20050218110
    Abstract: A method for manufacturing a wiring substrate includes the steps of (a) patterning a surface-active agent on a substrate having first and second areas to be remained on the first area; (b) removing residues of the surface-active agent in the second area by wet-etching with an alkali; (c) patterning a catalyst to be remained on one of the second area of the substrate and the surface-active agent; and (d) depositing a metal layer on the catalyst to thereby form a wiring.
    Type: Application
    Filed: March 28, 2005
    Publication date: October 6, 2005
    Inventors: Hidemichi Furihata, Satoshi Kimura, Minoru Marumo
  • Publication number: 20050218487
    Abstract: A method to deposit a metal layer only in a required portion, and to form wirings with a simple manufacture process. The method for manufacturing a wiring substrate includes the steps of: (a) forming a ground layer precursor having reactive groups including nitrogen atoms in first and second areas of a substrate; (b) irradiating light energy to remove the reactive groups from the ground layer precursor to thereby form a ground layer; (c) patterning a surface-active agent to be left on the first area of the substrate with the ground layer as a ground; (d) providing a catalyst at the surface-active agent; and (e) forming a wiring along the first area of the substrate by precipitating a metal layer to the catalyst.
    Type: Application
    Filed: March 28, 2005
    Publication date: October 6, 2005
    Inventors: Satoshi Kimura, Hidemichi Furihata
  • Publication number: 20050186699
    Abstract: A method of manufacturing a transistor includes the step of forming on a substrate a source electrode and drain electrode by selective electroless plating after patterning a charge control agent attached to the substrate using light, and the step of forming an organic semiconductor, a gate insulation layer, and a gate electrode.
    Type: Application
    Filed: February 18, 2005
    Publication date: August 25, 2005
    Applicant: Seiko Epson Corporation
    Inventors: Takeo Kawase, Satoshi Kimura, Hidemichi Furihata, Mitsuaki Harada
  • Publication number: 20050170622
    Abstract: A method for manufacturing a wiring substrate includes the steps of (a) irradiating a vacuum ultraviolet radiation on a second area of a substrate having a first area and the second area to thereby break down an interatomic bond in the second area of the substrate, (b) providing a catalyst in the first and second areas of the substrate, (c) washing the substrate to thereby remove a portion of the catalyst provided in the second area, and (d) depositing a metal layer on a portion of the catalyst remaining in the first area to thereby form a wiring composed of the metal layer along the first area.
    Type: Application
    Filed: February 3, 2005
    Publication date: August 4, 2005
    Inventors: Satoshi Kimura, Hidemichi Furihata, Minoru Marumo, Tomohiko Sogo
  • Publication number: 20050170652
    Abstract: A method for manufacturing a wiring substrate includes the steps of (a) providing a first surface-active agent in first and second areas and of a substrate, (b) providing a second surface-active agent in the first area of the substrate, (c) providing a catalyst on the second surface-active agent, and (d) depositing a metal layer on the catalyst to thereby form a wiring composed of the metal layer along the first area.
    Type: Application
    Filed: February 3, 2005
    Publication date: August 4, 2005
    Inventors: Hidemichi Furihata, Satoshi Kimura, Minoru Marumo
  • Publication number: 20050170079
    Abstract: A method for manufacturing a wiring substrate includes the steps of (a) providing a catalyst in first and second areas of a substrate, (b) irradiating a vacuum ultraviolet radiation to the second area of the substrate to thereby break down an interatomic bond in the second area of the substrate, (c) washing the substrate to thereby remove a portion of the catalyst provided in the second area, and (d) depositing a metal layer on a portion of the catalyst remaining in the first area to thereby form a wiring composed of the metal layer along the first area.
    Type: Application
    Filed: February 3, 2005
    Publication date: August 4, 2005
    Inventors: Hidemichi Furihata, Satoshi Kimura, Minoru Marumo