Abstract: A semiconductor memory device comprises: first conductive layers arranged in a first direction; a first semiconductor layer facing the first conductive layers; a second semiconductor layer facing the first conductive layers; second conductive layers arranged in the first direction; third conductive layers arranged in the first direction; a third semiconductor layer facing the second conductive layers and connected to the first semiconductor layer; a fourth semiconductor layer facing the third conductive layers and connected to the second semiconductor layer; a fourth conductive layer facing the third semiconductor layer; and a fifth conductive layer connected to the third conductive layers. A distance from a central axis of the third semiconductor layer to a central axis of the fourth semiconductor layer is larger than a distance from a central axis of the first semiconductor layer to a central axis of the second semiconductor layer.

Abstract: A semiconductor memory device comprises: a substrate; a first semiconductor portion provided separated from the substrate in a first direction intersecting a surface of the substrate, the first semiconductor portion extending in a second direction intersecting the first direction; a first gate electrode extending in the first direction; a first insulating portion which is provided between the first semiconductor portion and the first gate electrode, includes hafnium (Hf) and oxygen (O), and includes an orthorhombic crystal as a crystal structure; a first conductive portion provided between the first semiconductor portion and the first insulating portion; and a second insulating portion provided between the first semiconductor portion and the first conductive portion. An area of a facing surface of the first conductive portion facing the first semiconductor portion is larger than an area of a facing surface of the first conductive portion facing the first gate electrode.

Abstract: A semiconductor memory device includes a substrate, a semiconductor layer extending in a first direction, a first conductive layer extending in a second direction and opposed to the semiconductor layer, an electric charge accumulating layer disposed between the semiconductor layer and the first conductive layer, and a first contact electrode extending in the first direction and connected to the first conductive layer. The first contact electrode has one end in the first direction farther from the substrate than the first conductive layer, the other end in the first direction closer to the substrate than the first conductive layer. The first conductive layer includes a first part opposed to the semiconductor layer and a second part connected to the first contact electrode. The second part has a thickness in the first direction larger than a thickness in the first direction of the first part.

Abstract: Provided is a storage device according to an embodiment including: a stacked body including gate electrode layers stacked in a first direction; a semiconductor layer provided in the stacked body and extending in the first direction; and a gate insulating film provided between the semiconductor layer and the gate electrode layer, the gate insulating film having a first region disposed between the gate electrode layer and the semiconductor layer and a second region disposed between the two first regions adjacent to each other in the first direction, the gate insulating film containing a hafnium oxide, in which a first thickness of the first region in the second direction from the semiconductor layer toward the gate electrode layer is smaller than a second thickness of the second region in the second direction.

Abstract: A semiconductor memory device comprises: first conductive layers arranged in a first direction; a first semiconductor layer facing the first conductive layers; a second semiconductor layer facing the first conductive layers; second conductive layers arranged in the first direction; third conductive layers arranged in the first direction; a third semiconductor layer facing the second conductive layers and connected to the first semiconductor layer; a fourth semiconductor layer facing the third conductive layers and connected to the second semiconductor layer; a fourth conductive layer facing the third semiconductor layer; and a fifth conductive layer connected to the third conductive layers. A distance from a central axis of the third semiconductor layer to a central axis of the fourth semiconductor layer is larger than a distance from a central axis of the first semiconductor layer to a central axis of the second semiconductor layer.

Abstract: Provided is a storage device according to an embodiment including: a stacked body including gate electrode layers stacked in a first direction; a semiconductor layer provided in the stacked body and extending in the first direction; and a gate insulating film provided between the semiconductor layer and the gate electrode layer, the gate insulating film having a first region disposed between the gate electrode layer and the semiconductor layer and a second region disposed between the two first regions adjacent to each other in the first direction, the gate insulating film containing a hafnium oxide, in which a first thickness of the first region in the second direction from the semiconductor layer toward the gate electrode layer is smaller than a second thickness of the second region in the second direction.

Abstract: A semiconductor memory device comprises: a substrate; gate electrodes arranged in a first direction crossing a surface of the substrate; a first semiconductor layer including a first portion extending in the first direction and facing the plurality of gate electrodes, and, a second portion nearer to the substrate than the first portion; a gate insulating film provided between the gate electrode and the first portion of the first semiconductor layer, and, including a memory portion; and, a wiring portion provided between the substrate and the plurality of gate electrodes, connected to the second portion of the first semiconductor layer, and, extending in a second direction crossing the first direction. The wiring portion comprises a second semiconductor layer connected to the second portion of the first semiconductor layer. The second semiconductor layer includes a first crystal grain larger than a thickness in the first direction of the second semiconductor layer.

Abstract: A semiconductor memory device comprises: a substrate; a first semiconductor portion provided separated from the substrate in a first direction intersecting a surface of the substrate, the first semiconductor portion extending in a second direction intersecting the first direction; a first gate electrode extending in the first direction; a first insulating portion which is provided between the first semiconductor portion and the first gate electrode, includes hafnium (Hf) and oxygen (O), and includes an orthorhombic crystal as a crystal structure; a first conductive portion provided between the first semiconductor portion and the first insulating portion; and a second insulating portion provided between the first semiconductor portion and the first conductive portion. An area of a facing surface of the first conductive portion facing the first semiconductor portion is larger than an area of a facing surface of the first conductive portion facing the first gate electrode.

Abstract: A semiconductor memory device includes: a substrate; a plurality of first semiconductor portions arranged in a first direction intersecting a surface of the substrate; a first gate electrode extending in the first direction, the first gate electrode facing the plurality of first semiconductor portions from a second direction intersecting the first direction; a first insulating portion provided between the first semiconductor portions and the first gate electrode; a first wiring separated from the first gate electrode in the first direction; a second semiconductor portion connected to one end in the first direction of the first gate electrode and to the first wiring; a second gate electrode facing the second semiconductor portion; and a second insulating portion provided between the second semiconductor portion and the second gate electrode.

Abstract: A semiconductor memory device includes: a substrate; a plurality of first semiconductor portions arranged in a first direction intersecting a surface of the substrate; a first gate electrode extending in the first direction, the first gate electrode facing the plurality of first semiconductor portions from a second direction intersecting the first direction; a first insulating portion provided between the first semiconductor portions and the first gate electrode; a first wiring separated from the first gate electrode in the first direction; a second semiconductor portion connected to one end in the first direction of the first gate electrode and to the first wiring; a second gate electrode facing the second semiconductor portion; and a second insulating portion provided between the second semiconductor portion and the second gate electrode.

Abstract: A semiconductor memory device includes conductive layers and insulation layers alternately stacked along a first direction. A core member extends through the insulation layers and conductive layers. A semiconductor layer on an outer periphery of the core member has a first region facing a conductive layer of the stack and a second region adjacent to the first region and facing an insulation layer. The first region has a first thickness and a first impurity concentration. The second region has a second thickness that is greater than the first thickness and a second impurity concentration that is different from the first impurity concentration. A charge accumulation film is between the semiconductor layer and the conductive layer in a second direction crossing the first direction.

Abstract: A semiconductor memory device, including: a substrate; a plurality of first conductive layers arranged in a first direction intersecting a surface of the substrate; a channel semiconductor layer extending in the first direction and including a first portion facing the plurality of the first conductive layers and a second portion further from the substrate than the first portion; a memory layer arranged between the first portion of the channel semiconductor layer and the plurality of the first conductive layers and including a memory part capable of storing data; and a first semiconductor layer connected to the second portion of the channel semiconductor layer, the first semiconductor layer including crystalline semiconductor containing a first impurity, and the channel semiconductor layer including a crystal grain having a crystal grain size larger than a thickness thereof.

Abstract: A semiconductor memory device includes conductive layers and insulation layers alternately stacked along a first direction. A core member extends through the insulation layers and conductive layers. A semiconductor layer on an outer periphery of the core member has a first region facing a conductive layer of the stack and a second region adjacent to the first region and facing an insulation layer. The first region has a first thickness and a first impurity concentration. The second region has a second thickness that is greater than the first thickness and a second impurity concentration that is different from the first impurity concentration. A charge accumulation film is between the semiconductor layer and the conductive layer in a second direction crossing the first direction.

Abstract: A semiconductor memory device comprises: a substrate; gate electrodes arranged in a first direction crossing a surface of the substrate; a first semiconductor layer including a first portion extending in the first direction and facing the plurality of gate electrodes, and, a second portion nearer to the substrate than the first portion; a gate insulating film provided between the gate electrode and the first portion of the first semiconductor layer, and, including a memory portion; and, a wiring portion provided between the substrate and the plurality of gate electrodes, connected to the second portion of the first semiconductor layer, and, extending in a second direction crossing the first direction. The wiring portion comprises a second semiconductor layer connected to the second portion of the first semiconductor layer. The second semiconductor layer includes a first crystal grain larger than a thickness in the first direction of the second semiconductor layer.

Abstract: A semiconductor memory device according to an embodiment comprises a plurality of control gate electrodes, a first semiconductor layer, and a gate insulating layer. The plurality of control gate electrodes are arranged in a first direction that intersects a surface of a substrate. The first semiconductor layer extends in the first direction and faces side surfaces in a second direction intersecting the first direction, of the plurality of control gate electrodes. The gate insulating layer is provided between the control gate electrode and the first semiconductor layer. In addition, the first semiconductor layer includes: a first portion having a first plane orientation; and a second portion having a second plane orientation which is different from the first plane orientation.

Abstract: A semiconductor memory device, including: a substrate; a plurality of first conductive layers arranged in a first direction intersecting a surface of the substrate; a channel semiconductor layer extending in the first direction and including a first portion facing the plurality of the first conductive layers and a second portion further from the substrate than the first portion; a memory layer arranged between the first portion of the channel semiconductor layer and the plurality of the first conductive layers and including a memory part capable of storing data; and a first semiconductor layer connected to the second portion of the channel semiconductor layer, the first semiconductor layer including crystalline semiconductor containing a first impurity, and the channel semiconductor layer including a crystal grain having a crystal grain size larger than a thickness thereof.

Abstract: According to one embodiment, a memory device includes a first conductive layer, a second conductive layer, a first insulating layer and a first layer. The first conductive layer includes a first metal capable of forming a compound with silicon. The second conductive layer includes at least one selected from a group consisting of tungsten, molybdenum, platinum, tungsten nitride, molybdenum nitride, and titanium nitride. The first insulating layer is provided between the first conductive layer and the second conductive layer. The first layer is provided between the first insulating layer and the second conductive layer. The first layer includes silicon.

Abstract: A semiconductor memory device according to an embodiment comprises a plurality of control gate electrodes, a first semiconductor layer, and a gate insulating layer. The plurality of control gate electrodes are arranged in a first direction that intersects a surface of a substrate. The first semiconductor layer extends in the first direction and faces side surfaces in a second direction intersecting the first direction, of the plurality of control gate electrodes. The gate insulating layer is provided between the control gate electrode and the first semiconductor layer. In addition, the first semiconductor layer includes: a first portion having a first plane orientation; and a second portion having a second plane orientation which is different from the first plane orientation.

Abstract: According to one embodiment, a nonvolatile resistance change element includes a first electrode, a second electrode, a semiconductor layer and a first layer. The first electrode includes at least one of Ag, Ni, Co, Al, Zn, Ti, and Cu. The semiconductor layer is sandwiched between the first and second electrodes. The first layer is provided between the second electrode and the semiconductor layer and contains an element included in the semiconductor layer and at least one of Ag, Ni, and Co.

Abstract: According to one embodiment, a nonvolatile resistance change element includes a first electrode, a second electrode and a first layer. The first electrode includes a metal element. The second electrode includes an n-type semiconductor. The first layer is formed between the first electrode and the second electrode and includes a semiconductor element. The first layer includes a conductor portion made of the metal element. The conductor portion and the second electrode are spaced apart.