Patents by Inventor Hidenori Miyagawa
Hidenori Miyagawa has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 8971106Abstract: According to one embodiment, a nonvolatile semiconductor memory device includes a memory cell array and a control circuit. The memory cell array include the memory cells each including a variable resistance element in which a reset current flowing in a reset operation is smaller than a set current flowing in a set operation by not less than one order of magnitude. The control circuit performs the reset operation and the set operation for the memory cells. The control circuit performs the reset operation for all memory cells being in the low resistance state and connected to selected first interconnections and selected second interconnections.Type: GrantFiled: September 8, 2014Date of Patent: March 3, 2015Assignee: Kabushiki Kaisha ToshibaInventors: Akira Takashima, Hidenori Miyagawa, Shosuke Fujii, Daisuke Matsushita
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Publication number: 20140376303Abstract: According to one embodiment, a nonvolatile semiconductor memory device includes a memory cell array and a control circuit. The memory cell array include the memory cells each including a variable resistance element in which a reset current flowing in a reset operation is smaller than a set current flowing in a set operation by not less than one order of magnitude. The control circuit performs the reset operation and the set operation for the memory cells. The control circuit performs the reset operation for all memory cells being in the low resistance state and connected to selected first interconnections and selected second interconnections.Type: ApplicationFiled: September 8, 2014Publication date: December 25, 2014Applicant: KABUSHIKI KAISHA TOSHIBAInventors: Akira TAKASHIMA, Hidenori Miyagawa, Shosuke Fujii, Daisuke Matsushita
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Publication number: 20140353572Abstract: A resistance random access memory device according to an embodiment includes a first electrode, a second electrode and a variable resistance film provided between the first electrode and the second electrode. The second electrode includes material selected from the group consisting of silver, copper, zinc, gold, titanium, nickel, cobalt, tantalum, aluminum, and bismuth, alloys thereof, and silicides thereof. The variable resistance film includes silicon oxynitride. The variable resistance film includes a first resistance change layer having a first nitrogen concentration and a second resistance change layer having a second nitrogen concentration lower than the first nitrogen concentration.Type: ApplicationFiled: August 14, 2014Publication date: December 4, 2014Applicant: Kabushiki Kaisha ToshibaInventors: Riichiro Takaishi, Hidenori Miyagawa, Shosuke Fujii
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Publication number: 20140346434Abstract: According to one embodiment, a nonvolatile variable resistance element includes a first electrode, a second electrode, a variable resistance layer, and a dielectric layer. The second electrode includes a metal element. The variable resistance layer is arranged between the first electrode and the second electrode. A resistance change is reversibly possible in the variable resistance layer according to move the metal element in and out. The dielectric layer is inserted between the second electrode and the variable resistance layer and has a diffusion coefficient of the metal element smaller than that of the variable resistance layer.Type: ApplicationFiled: August 13, 2014Publication date: November 27, 2014Applicant: KABUSHIKI KAISHA TOSHIBAInventors: Hidenori MIYAGAWA, Shosuke FUJII, Akira TAKASHIMA, Daisuke MATSUSHITA
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Patent number: 8860182Abstract: A resistance random access memory device according to an embodiment includes a first electrode, a second electrode and a variable resistance film provided between the first electrode and the second electrode. The second electrode includes material selected from the group consisting of silver, copper, zinc, gold, titanium, nickel, cobalt, tantalum, aluminum, and bismuth, alloys thereof, and silicides thereof. The variable resistance film includes silicon oxynitride. The variable resistance film includes a first resistance change layer having a first nitrogen concentration and a second resistance change layer having a second nitrogen concentration lower than the first nitrogen concentration.Type: GrantFiled: September 6, 2013Date of Patent: October 14, 2014Assignee: Kabushiki Kaisha ToshibaInventors: Riichiro Takaishi, Hidenori Miyagawa, Shosuke Fujii
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Patent number: 8854874Abstract: According to one embodiment, a nonvolatile semiconductor memory device includes a memory cell array and a control circuit. The memory cell array include the memory cells each including a variable resistance element in which a reset current flowing in a reset operation is smaller than a set current flowing in a set operation by not less than one order of magnitude. The control circuit performs the reset operation and the set operation for the memory cells. The control circuit performs the reset operation for all memory cells being in the low resistance state and connected to selected first interconnections and selected second interconnections.Type: GrantFiled: August 14, 2013Date of Patent: October 7, 2014Assignee: Kabushiki Kaisha ToshibaInventors: Akira Takashima, Hidenori Miyagawa, Shosuke Fujii, Daisuke Matsushita
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Publication number: 20140284543Abstract: A resistance random access memory device according to an embodiment includes a first electrode, a second electrode, and a variable resistance portion placed between the first electrode and the second electrode. The variable resistance portion includes a first insulating layer, a second insulating layer, and a crystal layer that is placed between the first insulating layer and the second insulating layer, has a higher resistivity than the first electrode, and is crystalline.Type: ApplicationFiled: September 10, 2013Publication date: September 25, 2014Applicant: Kabushiki Kaisha ToshibaInventors: Takayuki Ishikawa, Shosuke Fujii, Hidenori Miyagawa, Hiroki Tanaka, Masumi Saitoh
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Publication number: 20140284544Abstract: A resistance random access memory device according an embodiment includes a first electrode, a second electrode and a resistance change layer. The first electrode includes a metal. The resistance change layer is provided between the first electrode and the second electrode. One of the metal is able to reversibly move within the resistance change layer. The second electrode is formed of a material ionizing less easily than the metal. The resistance change layer contains silicon, oxygen, and nitrogen, a nitrogen concentration of the resistance change layer is less than 46 atomic % and not less than 20 atomic %.Type: ApplicationFiled: September 10, 2013Publication date: September 25, 2014Applicant: Kabushiki Kaisha ToshibaInventors: Hidenori MIYAGAWA, Shosuke FUJII, Takayuki ISHIKAWA
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Publication number: 20140284541Abstract: A resistance random access memory device according to an embodiment includes a first electrode, a second electrode and a variable resistance film provided between the first electrode and the second electrode. The second electrode includes material selected from the group consisting of silver, copper, zinc, gold, titanium, nickel, cobalt, tantalum, aluminum, and bismuth, alloys thereof, and silicides thereof. The variable resistance film includes silicon oxynitride. The variable resistance film includes a first resistance change layer having a first nitrogen concentration and a second resistance change layer having a second nitrogen concentration lower than the first nitrogen concentration.Type: ApplicationFiled: September 6, 2013Publication date: September 25, 2014Applicant: KABUSHIKI KAISHA TOSHIBAInventors: Riichiro TAKAISHI, Hidenori Miyagawa, Shosuke Fujii
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Patent number: 8835896Abstract: According to one embodiment, a nonvolatile variable resistance element includes a first electrode, a second electrode, a variable resistance layer, and a dielectric layer. The second electrode includes a metal element. The variable resistance layer is arranged between the first electrode and the second electrode. A resistance change is reversibly possible in the variable resistance layer according to move the metal element in and out. The dielectric layer is inserted between the second electrode and the variable resistance layer and has a diffusion coefficient of the metal element smaller than that of the variable resistance layer.Type: GrantFiled: August 19, 2013Date of Patent: September 16, 2014Assignee: Kabushiki Kaisha ToshibaInventors: Hidenori Miyagawa, Shosuke Fujii, Akira Takashima, Daisuke Matsushita
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Patent number: 8772751Abstract: According to one embodiment, a memory device includes a first electrode including a crystallized SixGe1-x layer (0?x<1), a second electrode including a metal element, a variable resistance part between the first and second electrode, the part including an amorphous Si layer, and a control circuit controlling a filament in the amorphous Si layer, the filament including the metal element.Type: GrantFiled: September 16, 2011Date of Patent: July 8, 2014Assignee: Kabushiki Kaisha ToshibaInventors: Akira Takashima, Daisuke Matsushita, Takashi Yamauchi, Yuuichi Kamimuta, Hidenori Miyagawa
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Patent number: 8723152Abstract: A variable resistance memory according to an embodiment includes: a first wiring; a second wiring intersecting with the first wiring; a first electrode provided in an intersection region between the first wiring and the second wiring, the first electrode being connected to the first wiring; a second electrode connected to the second wiring, the second electrode facing to the first electrode; a variable resistance layer provided between the first electrode and the second electrode; and one of a first insulating layer and a first semiconductor layer formed at side portions of the second electrode. The one of the first insulating layer and the first semiconductor layer, and the second electrode form voids at the side portions of the second electrode.Type: GrantFiled: March 21, 2012Date of Patent: May 13, 2014Assignee: Kabushiki Kaisha ToshibaInventors: Yoshifumi Nishi, Hidenori Miyagawa, Daisuke Matsushita, Jun Fujiki, Takeshi Imamura
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Patent number: 8664632Abstract: According to one embodiment, a memory device includes a first electrode, a second electrode, and a variable resistance film. The variable resistance film is connected between the first electrode and the second electrode. The first electrode includes a metal contained in a matrix made of a conductive material. A cohesive energy of the metal is lower than a cohesive energy of the conductive material. A concentration of the metal at a central portion of the first electrode in a width direction thereof is higher than concentrations of the metal in two end portions of the first electrode in the width direction.Type: GrantFiled: August 30, 2012Date of Patent: March 4, 2014Assignee: Kabushiki Kaisha ToshibaInventors: Daisuke Matsushita, Shosuke Fujii, Yoshifumi Nishi, Akira Takashima, Takayuki Ishikawa, Hidenori Miyagawa, Takashi Haimoto, Yusuke Arayashiki, Hideki Inokuma
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Publication number: 20130328008Abstract: According to one embodiment, a nonvolatile resistance change element includes a first electrode, a second electrode and a first layer. The first electrode includes a metal element. The second electrode includes an n-type semiconductor. The first layer is formed between the first electrode and the second electrode and includes a semiconductor element. The first layer includes a conductor portion made of the metal element. The conductor portion and the second electrode are spaced apart.Type: ApplicationFiled: August 15, 2013Publication date: December 12, 2013Applicant: Kabushiki Kaisha ToshibaInventors: Hidenori Miyagawa, Akira Takashima, Shosuke Fuji
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Publication number: 20130329485Abstract: According to one embodiment, a nonvolatile semiconductor memory device includes a memory cell array and a control circuit. The memory cell array include the memory cells each including a variable resistance element in which a reset current flowing in a reset operation is smaller than a set current flowing in a set operation by not less than one order of magnitude. The control circuit performs the reset operation and the set operation for the memory cells. The control circuit performs the reset operation for all memory cells being in the low resistance state and connected to selected first interconnections and selected second interconnections.Type: ApplicationFiled: August 14, 2013Publication date: December 12, 2013Applicant: KABUSHIKI KAISHA TOSHIBAInventors: Akira TAKASHIMA, Hidenori Miyagawa, Shosuke Fujii, Daisuke Matsushita
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Publication number: 20130328009Abstract: According to one embodiment, a nonvolatile variable resistance element includes a first electrode, a second electrode, a variable resistance layer, and a dielectric layer. The second electrode includes a metal element. The variable resistance layer is arranged between the first electrode and the second electrode. A resistance change is reversibly possible in the variable resistance layer according to move the metal element in and out. The dielectric layer is inserted between the second electrode and the variable resistance layer and has a diffusion coefficient of the metal element smaller than that of the variable resistance layer.Type: ApplicationFiled: August 19, 2013Publication date: December 12, 2013Applicant: Kabushiki Kaisha ToshibaInventors: Hidenori MIYAGAWA, Shosuke Fujii, Akira Takashima, Daisuke Matsushita
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Publication number: 20130306932Abstract: According to one embodiment, a nonvolatile resistance change element includes a first electrode, a second electrode, a semiconductor layer and a first layer. The first electrode includes at least one of Ag, Ni, Co, Al, Zn, Ti, and Cu. The semiconductor layer is sandwiched between the first and second electrodes. The first layer is provided between the second electrode and the semiconductor layer and contains an element included in the semiconductor layer and at least one of Ag, Ni, and Co.Type: ApplicationFiled: July 31, 2013Publication date: November 21, 2013Applicant: KABUSHIKI KAISHA TOSHIBAInventors: Shosuke FUJII, Hidenori MIYAGAWA, Takashi YAMAUCHI
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Publication number: 20130234097Abstract: According to one embodiment, a nonvolatile resistance change element includes a first electrode, a second electrode, a first layer and a second layer. The second electrode contains at least one metal element selected from Ag, Cu, Ni, Co, Al, and Ti. The first layer is arranged between the first electrode and the second electrode. The second layer is arranged between the first electrode and the first layer. A diffusion coefficient of the metal element in the second layer is larger than a diffusion coefficient of the metal element in the first layer.Type: ApplicationFiled: September 5, 2012Publication date: September 12, 2013Inventors: Shosuke FUJII, Hidenori Miyagawa, Reika Ichihara
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Publication number: 20130228736Abstract: According to one embodiment, a memory device includes a first electrode, a second electrode, and a variable resistance film. The variable resistance film is connected between the first electrode and the second electrode. The first electrode includes a metal contained in a matrix made of a conductive material. A cohesive energy of the metal is lower than a cohesive energy of the conductive material. A concentration of the metal at a central portion of the first electrode in a width direction thereof is higher than concentrations of the metal in two end portions of the first electrode in the width direction.Type: ApplicationFiled: August 30, 2012Publication date: September 5, 2013Applicant: Kabushiki Kaisha ToshibaInventors: Daisuke MATSUSHITA, Shosuke Fujii, Yoshifumi Nishi, Akira Takashima, Takayuki Ishikawa, Hidenori Miyagawa, Takashi Haimoto, Yusuke Arayashiki, Hideki Inokuma
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Publication number: 20130037776Abstract: A variable resistance memory according to an embodiment includes: a first wiring; a second wiring intersecting with the first wiring; a first electrode provided in an intersection region between the first wiring and the second wiring, the first electrode being connected to the first wiring; a second electrode connected to the second wiring, the second electrode facing to the first electrode; a variable resistance layer provided between the first electrode and the second electrode; and one of a first insulating layer and a first semiconductor layer formed at side portions of the second electrode. The one of the first insulating layer and the first semiconductor layer, and the second electrode form voids at the side portions of the second electrode.Type: ApplicationFiled: March 21, 2012Publication date: February 14, 2013Applicant: Kabushiki Kaisha ToshibaInventors: Yoshifumi NISHI, Hidenori MIYAGAWA, Daisuke MATSUSHITA, Jun FUJIKI, Takeshi IMAMURA