Abstract: An object of the invention is to provide a nonvolatile semiconductor memory device and an erase method for a memory cell array that have high degree of freedom and that are capable of quickly and securely implementing data erase and reprogramming. In a memory cell array, memory cells each configured of a variable resistor element for storing information through variations in electric resistance and a selected transistor are arranged in a matrix, and word lines (WL1, . . . , WLm) and bit lines (BL1, . . . , BLn) are arranged to select a predetermined memory cell. For the memory cell array, erase means is provided that sets the electric resistance of the variable resistor element to a predetermined erased state by applying voltage under a predetermined application condition to the word line (WL), bit line (BL), and source line (SL). The erase means switches between a batch-erase mode and an individual-erase mode.

Abstract: A semiconductor capacitor device has two pairs of first and second MIM capacitors on a semiconductor substrate. The paired first and second MIM capacitors include respective capacitor dielectric films having different compositions. Also, the paired first and second MIM capacitors are connected in inverse parallel fashion, with an upper electrode of the first MIM capacitor being connected with a lower electrode of the second MIM capacitor and with a lower electrode of the first MIM capacitor being connected with an upper electrode of the second MIM capacitor. Furthermore, the two first MIM capacitors are electrically connected in inverse parallel with each other, and the two second MIM capacitors are also electrically connected in inverse parallel with each other. This arrangement facilitates mutual counteraction of the voltage dependences of the two pairs of first and second MIM capacitors so as to make the voltage dependence of the capacitance of the capacitor device small.

Abstract: A semiconductor device comprises: gate electrode formed on a semiconductor substrate through the intervention of a gate insulating film; and a source/drain region provided with a silicide film on its surface and formed in the semiconductor substrate, wherein the source/drain region has an LDD region whose surface is partially or entirely tapered and an interface between the semiconductor substrate and the silicide film in the source/drain region is located higher than a surface of the semiconductor substrate below the gate electrode.

Abstract: A semiconductor capacitor device has paired first and second MIM capacitors on a semiconductor substrate. The first and second MIM capacitors include respective capacitor dielectric films having different compositions. Furthermore, upper electrodes and lower electrodes of the first and second MIM capacitors are connected in inverse parallel fashion. This arrangement facilitates mutual counteraction of the voltage dependences of the first and second MIM capacitors so as to make the voltage dependence of the capacitance of the capacitor device small.

Abstract: A semiconductor device comprises: gate electrode formed on a semiconductor substrate through the intervention of a gate insulating film; and a source/drain region provided with a silicide film on its surface and formed in the semiconductor substrate, wherein the source/drain region has an LDD region whose surface is partially or entirely tapered and an interface between the semiconductor substrate and the silicide film in the source/drain region is located higher than a surface of the semiconductor substrate below the gate electrode.