Abstract: A data processing system includes an input data processing unit, an intermediate data generation unit, and an output data generation unit. The input data processing unit acquires input data, and converts the input data according to a conversion rule. One example of the conversion rule is to increase the number of values included in the input data by adding dummy data to the input data. The intermediate data generation unit generates intermediate data by processing the input data after the conversion. The intermediate data are, for example, a plurality of rows and/or a plurality of columns of data formed of a plurality of values. The intermediate data include a significant value (i.e., a value desired to be acquired) and a value being a dummy. The output data generation unit generates output data by selecting the significant value of the intermediate data generated by the intermediate data generation unit.

Abstract: A remaining capacity estimation apparatus includes a storage processing unit and a calculation unit. The storage processing unit acquires a model from a model generation apparatus and stores the model in a model storage unit. When data for updating the model are acquired from the model generation apparatus, the storage processing unit updates the model stored in the model storage unit. The calculation unit calculates a remaining capacity of a storage battery managed by the remaining capacity estimation apparatus by using the model stored in the model storage unit. At this time, data (measurement data for calculation) input to the model include a current, a voltage, and a temperature of the storage battery. When the input data when generating the model are only a current, a voltage, and a temperature, the measurement data for calculation are only a current, a voltage, and a temperature.

Abstract: A deterioration estimation apparatus includes a storage processing unit and a calculation unit. The storage processing unit acquires a plurality of models from a model generation apparatus, and stores the models in a model storage unit. A plurality of models are generated by performing machine-learning on training data, the training data using, as input values, measurement data for training indicating a result of measuring a state of a storage battery when the number of charge and discharge times is ?i to ?j (where j?i), and using, as a target value, SOH indicating a deterioration state of the storage battery when the number of charge and discharge times is ? (where ?>?j). The calculation unit uses a plurality of models stored in a model storage unit to calculate an estimation result of transition of SOH of a storage battery managed by the deterioration estimation apparatus.

Abstract: A power amplifier of the present invention comprises MOS transistor (1) having a gate length of 180 nm or less, and output matching circuit (5) connected to a drain terminal of MOS transistor (1). Also, MOS transistor (1) is applied with voltage Vd_n normalized by a voltage value allowable in a DC state as a drain-source voltage, where Vd_n is in a range of 0.5 to 0.9. ZL (=RH+j·XL) represents a value equal to a load impedance when viewing the output matching circuit (5) from the drain terminal normalized by gate width W (mm) of MOS transistor (1), and a real part (RL) of the ZL is RL>0.64×Vd_n+0.19 (?·mm), and RL<0.64×Vd_n+1.73 (?·mm).

Abstract: A radio communications device includes a transmitter, a receiver, a propagation detecting unit, and a symbol rate setting unit. The receiver has a plurality of antennas, a plurality of transmitting circuits, and a transmission signal processing circuit. The transmission signal processing circuit has a modulator, and modulates data input transmission data in modulator to output the modulated data as transmission signal to the transmitting circuits. The receiver has a plurality of antennas, a plurality of receiving circuits, and a reception signal processing circuit. The reception signal processing circuit has a demodulator, demodulates reception signals input from the receiving circuits in demodulator to generate reception data. The propagation detecting unit detects propagation state of radio waves. The symbol rate setting unit selects a symbol to be communicated from a plurality of symbol rates based on the detected propagating state and sets the selected symbol rate to the modulator and to the demodulator.

Abstract: A field effect transistor (100) exhibiting good performance at high voltage operation and high frequency includes a first field plate electrode (116) and a second field plate electrode (118). The second field plate electrode includes a shielding part (119) located in the region between the first field plate electrode and a drain electrode (114), and serves to shield the first field plate electrode from the drain electrode. When in the cross sectional view in the gate length direction, the length in the gate length direction of an overlap region where the second field plate electrode (118) overlap the upper part of a structure including the first field plate electrode and a gate electrode (113) is designated as Lol, and the gate length is Lg, the relation expressed as 0 ?Lol/Lg?1 holds.

Abstract: A field effect transistor includes a layer structure made of compound semiconductor (111) provided on a semiconductor substrate (110) made of GaAs or InP, as an operation layer, and employs a first field plate electrode (116) and a second field plate electrode (118). The second field plate electrode includes a shielding part (119) located in the region between the first field plate electrode and a drain electrode (114), and serves to shield the first field plate electrode from the drain electrode. When, in the cross sectional view in the gate length direction, the length in the gate length direction of an overlap region, in which the second field plate electrode overlaps the upper part of a structure composed of the first field plate electrode and a gate electrode (113), is designated as Lol, and the gate length is Lg, the relation expressed as 0?Lol/Lg?1 holds.

Abstract: A power amplifier of the present invention comprises MOS transistor (1) having a gate length of 180 nm or less, and output matching circuit (5) connected to a drain terminal of MOS transistor (1). Also, MOS transistor (1) is applied with voltage Vd_n normalized by a voltage value allowable in a DC state as a drain-source voltage, where Vd_n is in a range of 0.5 to 0.9. ZL (=RH+j·XL) represents a value equal to a load impedance when viewing the output matching circuit (5) from the drain terminal normalized by gate width W (mm) of MOS transistor (1), and a real part (RL) of the ZL is RL>0.64×Vd_n+0.19 (?· mm), and RL<0.64×Vd_n+1.73 (?· mm).

Abstract: A field effect transistor (100) exhibiting good performance at high voltage operation and high frequency includes a first field plate electrode (116) and a second field plate electrode (118). The second field plate electrode includes a shielding part (119) located in the region between the first field plate electrode and a drain electrode (114), and serves to shield the first field plate electrode from the drain electrode. When in the cross sectional view in the gate length direction, the length in the gate length direction of an overlap region where the second field plate electrode (118) overlap the upper part of a structure including the first field plate electrode and a gate electrode (113) is designated as Lol, and the gate length is Lg, the relation expressed as 0?Lol/Lg?1 holds.

Abstract: A field effect transistor includes a layer structure made of compound semiconductor (111) provided on a semiconductor substrate (110) made of GaAs or InP, as an operation layer, and employs a first field plate electrode (116) and a second field plate electrode (118). The second field plate electrode includes a shielding part (119) located in the region between the first field plate electrode and a drain electrode (114), and serves to shield the first field plate electrode from the drain electrode. When, in the cross sectional view in the gate length direction, the length in the gate length direction of an overlap region, in which the second field plate electrode overlaps the upper part of a structure composed of the first field plate electrode and a gate electrode (113), is designated as Lol, and the gate length is Lg, the relation expressed as 0?Lol/Lg?1 holds.

Abstract: A radio communications device includes a transmitter, a receiver, a propagation detecting unit, and a symbol rate setting unit. The receiver has a plurality of antennas, a plurality of transmitting circuits, and a transmission signal processing circuit. The transmission signal processing circuit has a modulator, and modulates data input transmission data in modulator to output the modulated data as transmission signal to the transmitting circuits. The receiver has a plurality of antennas, a plurality of receiving circuits, and a reception signal processing circuit. The reception signal processing circuit has a demodulator, demodulates reception signals input from the receiving circuits in demodulator to generate reception data. The propagation detecting unit detects propagation state of radio waves. The symbol rate setting unit selects a symbol to be communicated from a plurality of symbol rates based on the detected propagating state and sets the selected symbol rate to the modulator and to the demodulator.

Abstract: A semiconductor device includes a sub-collector layer, a collector layer, a base layer, an emitter layer, and an emitter cap layer, which are sequentially laminated on a substrate. It also includes an emitter electrode, a base electrode, and a collector electrode, which are respectively formed on the emitter cap layer, the base layer, and the sub-collector layer. The sub-collector layer is made up of a first sub-collector layer adjacent to the substrate and a second sub-collector layer adjacent to the collector layer. In the area between adjacent device elements, the first sub-collector layer has an element insulating region created by ion implantation, and the second sub-collector layer has a recess-shaped element insulating region.

Abstract: A heterojunction bipolar transistor of the present invention is produced from a wafer including a substrate and a collector layer of a first conductivity type, a base layer of a second conductivity type and an emitter layer of the first conductivity type sequentially laminated on the substrate in this order. First, the wafer is etched up to a preselected depth of the collector layer via a first photoresist, which is formed at a preselected position on the emitter layer, serving as a mask. Subsequently, the collector layer etched with at least the sidewalls of the base layer and collector layer, which are exposed by the first etching step, and a second photoresist covering part of the surface of the collector layer contiguous with the sidewalls serving as a mask.

Abstract: A semiconductor device includes a sub-collector layer, a collector layer, a base layer, an emitter layer, and an emitter cap layer, which are sequentially laminated on a substrate. It also includes an emitter electrode, a base electrode, and a collector electrode, which are respectively formed on the emitter cap layer, the base layer, and the sub-collector layer. The sub-collector layer is made up of a first sub-collector layer adjacent to the substrate and a second sub-collector layer adjacent to the collector layer. In the area between adjacent device elements, the first sub-collector layer has an element insulating region created by ion implantation, and the second sub-collector layer has a recess-shaped element insulating region.

Abstract: A heterojunction bipolar transistor has a raised breakdown voltage and restrains the rising characteristic of IC-VCE characteristic from degrading. The collector region includes first, second, and third collector layers of semiconductor. The first collector layer is made of a doped or undoped semiconductor in such a way as to contact the sub-collector region. The second collector layer is made of a doped or undoped semiconductor having a narrower band gap than the first collector layer in such a way as to contact the base region. The third collector layer has a higher doping concentration than the second collector layer in such a way as to be located between or sandwiched by the first collector layer and the second collector layer.

Abstract: A semiconductor device of the present invention includes a systematic structure layer of first conductivity type and having a systematically arranged structure. The systematic structure layer is formed on a collector contact layer of first conductivity type, which is connected to collector electrodes. A compensation layer of first conductivity type is formed on the systematic structure layer. A collector layer of first conductivity type is formed on the compensation layer. A base layer is formed on the collector layer and connected to base electrodes. An emitter layer is formed on the base electrode and connected to an emitter electrode. The semiconductor device reduces collector resistance and thereby improves reliability.

Abstract: A heterojunction bipolar transistor of the present invention is produced from a wafer including a substrate and a collector layer of a first conductivity type, a base layer of a second conductivity type and an emitter layer of the first conductivity type sequentially laminated on the substrate in this order. First, the wafer is etched up to a preselected depth of the collector layer via a first photoresist, which is formed at a preselected position on the emitter layer, serving as a mask. Subsequently, the collector layer etched with at least the sidewalls of the base layer and collector layer, which are exposed by the first etching step, and a second photoresist covering part of the surface of the collector layer contiguous with the sidewalls serving as a mask.

Abstract: A heterojunction bipolar transistor has a raised breakdown voltage and restrains the rising characteristic of IC-VCE characteristic from degrading. The collector region includes first, second, and third collector layers of semiconductor. The first collector layer is made of a doped or undoped semiconductor in such a way as to contact the sub-collector region. The second collector layer is made of a doped or undoped semiconductor having a narrower band gap than the first collector layer in such a way as to contact the base region. The third collector layer has a higher doping concentration than the second collector layer in such a way as to be located between or sandwiched by the first collector layer and the second collector layer.

Abstract: A heterojunction bipolartansistor is fabricated on a semi-insulating substrate, and has a mesa structure, wherein an emitter signal line of titanium-platinum-gold alloy is held in contact with the collector layer as well as the emitter layer for forming a Schottky barrier diode connected between the emitter and the collector so that surge current flows before damage of the p-n junction of the heterojunction bipolar transistor.

Abstract: A heterojunction bipolar transistor and a protective PIN diode are implemented by two multi-layered compound semiconductor structures epitaxially grown on respective regions of a semi-insulating substrate; the entire upper surface of the base layer is covered with the emitter layer, and the base electrode on the emitter layer projects through the emitter layer into the base layer; although the two multi-layered compound semiconductor structures are covered with a passivation layer, the emitter layer prevents the base layer from direct contact with the passivation layer so that leakage current hardly flows between the base and the emitter.