Abstract: A heterojunction bipolar transistor has a multi-layered compound semi-conductor structure consisting of a sub-collector layer, a collector layer, a base layer, an emitter layer and an emitter cap layer, and a heavily doped extremely narrow delta-doped sheet region is formed in a surface portion of the sub-collector layer, wherein an emitter electrode, a base electrode and a collector electrode are formed on the emitter cap layer, base layer and the heavily-doped extremely narrow delta-doped sheet region so that the collector contact resistance is reduced without sacrifice of the current gain and reliability of transistor.

Abstract: A semiconductor device of the present invention includes a systematic structure layer of first conductivity type and having a systematically arranged structure. The systematic structure layer is formed on a collector contact layer of first conductivity type, which is connected to collector electrodes. A compensation layer of first conductivity type is formed on the systematic structure layer. A collector layer of first conductivity type is formed on the compensation layer. A base layer is formed on the collector layer and connected to base electrodes. An emitter layer is formed on the base electrode and connected to an emitter electrode. The semiconductor device reduces collector resistance and thereby improves reliability.

Abstract: A heterojunction bipolar transistor of the present invention is produced from a wafer including a substrate and a collector layer of a first conductivity type, a base layer of a second conductivity type and an emitter layer of the first conductivity type sequentially laminated on the substrate in this order. First, the wafer is etched up to a preselected depth of the collector layer via a first photoresist, which is formed at a preselected position on the emitter layer, serving as a mask. Subsequently, the collector layer etched with at least the sidewalls of the base layer and collector layer, which are exposed by the first etching step, and a second photoresist covering part of the surface of the collector layer contiguous with the sidewalls serving as a mask.

Abstract: A heterojunction bipolar transistor is composed of a substrate, a collector layer covering the substrate, a base layer formed on the collector layer, an emitter layer formed on the base layer, and an emitter contacting semiconductor layer formed on the emitter layer. The base layer is doped with a first conductive type dopant. The emitter layer is formed of a mixed crystal of first and second compound semiconductors, and doped with a second conductive type dopant. The emitter contacting semiconductor layer is doped with the second conductive type dopant. The emitter layer includes a superlattice layer connected to the base layer, and a disordered layer connected to the emitter contacting semiconductor layer. The first and second compound semiconductors are layered to form a superlattice in the superlattice layer, and the first and second compound semiconductors are irregularly layered in the disordered layer.

Abstract: The bipolar transistor includes an emitter layer at least a part of which is composed of AlGaAs, a collector layer at least a part of which is composed of GaAs, a base contact layer disposed in at least a part of an area between a base electrode and a base layer, and a base layer at least a part of which is composed of an InGaAs graded layer in which the concentration of In gradually increases from an emitter-base junction towards a base-collector junction.

Abstract: A heterojunction bipolar transistor has an n-type emitter layer of aluminum gallium arsenide and a beryllium doped base layer forming a heterojunction together with the n-type emitter layer, and the base layer is associated with a heavily doped carbon doped base region so that the beryllium content is restricted below the critical value for preventing the emitter layer from undesirable beryllium diffusion.

Abstract: On a semi-insulating substrate, an emitter layer (or a collector layer), a base layer, a compound semiconductor layer containing In and a collector layer (or an emitter layer) are provided. The collector layer (or the emitter layer) is patterned to form a collector region (or an emitter region). When the base surface is revealed by a reactive ion beam etching, the etching will be stopped at the compound semiconductor layer that contains In. Consequently, the nonuniformity in the base resistance that depends on the thickness of the base lead-out region can be reduced.

Abstract: On a semi-insulating substrate, an emitter layer (or a collector layer), a base layer, a compound semiconductor layer containing In and a collector layer (or an emitter layer) are provided. The collector layer (or the emitter layer) is patterned to form a collector region (or an emitter region). When the base surface is revealed by a reactive ion beam etching, the etching will be stopped at the compound semiconductor layer that contains In. Consequently, the nonuniformity in the base resistance that depends on the thickness of the base lead-out region can be reduced.

Abstract: A method of selective epitaxial growth for compound semiconductor includes the steps of forming a layer of group IV element semiconductor, such as Ge, with a predetermined pattern on a compound semiconductor substrate and forming a compound semiconductor layer selectively on the compound semiconductor substrate by alternately supplying a gas of compound containing a group III or II element, such as trimethylgallium, triethylgallium and triisobutylaluminum, and a gas of compound containing a group V or VI element, such as AsH.sub.3, onto both surface of the layer of group IV element semiconductor and the compound semiconductor substrate. Another semiconductor layer of group IV element semiconductor or compound semiconductor may be formed on the layer of group IV element semiconductor by organometallic vapor phase epitaxy or MBE.