Abstract: A stereo camera apparatus includes a housing, a first camera unit attached to the housing, a second camera unit attached to the housing, a processing device that performs image processing by using captured images acquired by capturing of the first camera unit and the second camera unit, and a circuit board on which the processing device is mounted. In the housing, a base length direction of the first camera unit and the second camera unit is a longitudinal direction, the housing and the circuit board are bonded to each other by an adhesive, and in a region in the housing, onto which the adhesive is applied, a length in the base line length direction is shorter than a length in an orthogonal direction that is a direction perpendicular to the base length direction.

Abstract: A substrate for a composite membrane includes a microporous polyolefin membrane for carrying a hydrophilic resin compound within the pores of the microporous membrane wherein: the average pore diameter is 1 nm to 50 nm; the porosity is 50% to 78%; the membrane thickness is 1 ?m to 12 ?m; and, when a mixed solution of ethanol and water (volume ratio 1/2) is dripped onto a surface of the microporous polyolefin membrane which has not undergone hydrophilization treatment, the contact angle ?1 between the droplet and the surface is 0 to 90 degrees 1 second after the dripping, and the contact angle ?2 between the droplet and the surface is 0 to 70 degrees 10 minutes after the dripping, and the rate of change of the contact angle ((?1??2)/?1×100) is 10 to 50%.

Abstract: A grindstone includes abrasive grains and a binder for fixing the abrasive grains, and the binder contains a spherical filler for reinforcing the bonding material.

Abstract: Apparatus and methods are disclosed, including stacked die devices and systems. Example stacked die devices and methods include an array of interconnect pillars that includes more than one pillar height. Example stacked die devices and methods include an array of interconnect pillars that includes a pillar height distribution mapped to a known warpage profile.

Abstract: Apparatus and methods are disclosed, including transistors, semiconductor devices and systems. Example semiconductor devices and methods include a first transmission line and a second transmission line located over one another. A via is shown connecting the first transmission line and a second transmission line wherein a first side of the via and a side of the second transmission line are coplanar. A via is also shown connecting the first transmission line and a second transmission line wherein the second transmission line tapers downward from a line width to a via width.

Abstract: Disclosed herein is a method that includes: forming a mask layer on a semiconductor substrate; forming a photoresist on the mask layer; performing non-uniform exposure on the photoresist to provide a first patterned photoresist which includes a first region where the photoresist is removed to expose the mask layer and a second region where a part of the photoresist remains; first etching using the first patterned photoresist to remove the mask layer in the first region and form a first trench in the first region of the semiconductor substrate; second etching to provide a second patterned photoresist which includes the second region where the photoresist is removed; third etching using the second patterned photoresist to remove the mask layer in the second region; and fourth etching to deepen the first trench in the first region and form a second trench shallower than the first trench in the second region.

Abstract: Apparatuses and methods for manufacturing chips are described. An example method includes: forming at least one first dielectric layer above a substrate; forming at least one second dielectric layer above the first dielectric layer; forming a cover layer above the at least one second dielectric layer; forming a groove above the substrate by etching; covering at least an edge surface of the at least one first dielectric layer in the groove with a liner including polymer; forming a hole through the cover layer and a portion of the at least one second dielectric layer; depositing a conductive layer in the hole, on the cover layer and the liner; and forming a conductive pillar on the conductive layer in the hole by electroplating.

Abstract: A semiconductor device includes a semiconductor substrate; and a multilevel wiring structure on the semiconductor substrate, the multilevel wiring structure including at least an intermediate metal layer over the semiconductor substrate and an uppermost metal layer over the intermediate metal layer, and the multilevel wiring structure being divided into a main circuit portion and a scribe portion surrounding the main circuit portion; wherein the scribe portion of the multilevel wiring layer includes at least a metal pad exposed in the intermediate metal layer.

Abstract: A semiconductor structure includes an opening formed in a surface of an insulating layer, and a lower metal layer on the surface of the insulating layer, and sidewalls and a bottom surface of the opening in the surface of the insulating layer. The sidewalls are tapered inwardly from the surface of the insulating layer to the bottom surface of the opening by a taper angle of between 10 degrees and 45 degrees.

Abstract: Apparatuses and methods for manufacturing chips are described. An example method includes: forming at least one first dielectric layer above a substrate; forming at least one second dielectric layer above the first dielectric layer; forming a cover layer above the at least one second dielectric layer; forming a groove above the substrate by etching; covering at least an edge surface of the at least one first dielectric layer in the groove with a liner; forming a hole through the cover layer and a portion of the at least one second dielectric layer; depositing a conductive layer in the hole, on the cover layer and the liner; and forming a conductive pillar on the conductive layer in the hole by electroplating.

Abstract: A semiconductor device includes a semiconductor substrate; a first insulating film and a second insulating film provided above the semiconductor substrate; a low-k film provided between the first insulating film and the second insulating film; an element formation region in which elements included in an electric circuit are formed in the semiconductor substrate; a scribe region provided around the element formation region; a cut portion provided on the outer periphery of the scribe region; and a groove formed between the cut portion and the element formation region, wherein the groove penetrates through the low-k film.

Abstract: Apparatuses and methods for manufacturing chips are described. An example method includes: removing a first portion of a cover layer and at least one dielectric layer under the first portion of the cover layer in a cut region between chips to form a groove, and forming a support structure including a second portion of the cover layer and the at least one dielectric layer under the second portion of the cover layer in the cut region; removing a third portion of the cover layer in one of the chips and a portion of the at least one dielectric layer under the third portion of the cover layer to form an hole on the first chip; depositing a conductive layer to cover the cover layer and the hole; forming a conductive pillar on the conductive layer in the hole; and removing the conductive layer on the cover layer and an edge surface of the hole.

Abstract: A semiconductor device includes a first layer including a plurality of wirings arranged in line and space layout and a second layer including a pad electrically connected to at least one of the wirings, wherein the wirings and the pads are patterned by different lithographic processes.

Abstract: A method including forming an insulating film over first, second, third and fourth regions of a semiconductor substrate; forming a polyimide film on the insulating film; and patterning the polyimide film with a lithography method using a photomask including at least a first region of a first transmittance rate, a second region of a second transmittance rate, a third region having a shading material, and a fourth region, wherein the first, second, third and fourth regions of the photomask correspond to the first, second, third and fourth regions of the semiconductor substrate, respectively.

Abstract: According to one or more embodiments, a method of manufacturing a semiconductor device including a plurality of main circuit regions arranged in a matrix and a scribe region provided between the main circuit regions is provided. The method includes: forming a first insulating film; forming a low-k film; forming a plurality of penetrating portions penetrating through the low-k film; and forming a second insulating film under low-coverage film-forming conditions to form cavities in the plurality of through-holes.

Abstract: A semiconductor device includes: a substrate; a memory cell region over the substrate; a peripheral region over the substrate, the peripheral region being adjacent to the memory cell region; and a plurality of first and second word-lines extending across the memory cell region and the peripheral region; wherein the plurality of first word-lines and the plurality of second word-lines are arranged alternately with each other; and wherein the length of the first word-line in the peripheral region is longer than the length of the second word-line in the peripheral region.

Abstract: Apparatuses and methods for manufacturing chips are described. An example method includes: removing a first portion of a cover layer and at least one dielectric layer under the first portion of the cover layer in a cut region between chips to form a groove, and forming a support structure including a second portion of the cover layer and the at least one dielectric layer under the second portion of the cover layer in the cut region; removing a third portion of the cover layer in one of the chips and a portion of the at least one dielectric layer under the third portion of the cover layer to form an hole on the first chip; depositing a conductive layer to cover the cover layer and the hole; forming a conductive pillar on the conductive layer in the hole; and removing the conductive layer on the cover layer and an edge surface of the hole.

Abstract: Apparatuses and methods for manufacturing chips are described. An example method includes: forming at least one first dielectric layer above a substrate; forming at least one second dielectric layer above the first dielectric layer; forming a cover layer above the at least one second dielectric layer; forming a groove above the substrate by etching; covering at least an edge surface of the at least one first dielectric layer in the groove with a liner including polymer; forming a hole through the cover layer and a portion of the at least one second dielectric layer; depositing a conductive layer in the hole, on the cover layer and the liner; and forming a conductive pillar on the conductive layer in the hole by electroplating.

Abstract: Apparatuses and methods for manufacturing chips are described. An example method includes: forming at least one first dielectric layer above a substrate; forming at least one second dielectric layer above the first dielectric layer; forming a cover layer above the at least one second dielectric layer; forming a groove above the substrate by etching; covering at least an edge surface of the at least one first dielectric layer in the groove with a liner; forming a hole through the cover layer and a portion of the at least one second dielectric layer; depositing a conductive layer in the hole, on the cover layer and the liner; and forming a conductive pillar on the conductive layer in the hole by electroplating.

Abstract: A semiconductor device includes a main circuit region; and a scribe region surrounding the main circuit region; wherein the main circuit region and the scribe region comprises first and second insulating films and a low-k film formed therebetween; and wherein the low-k film of the scribe region includes a plurality of cavities lining along a border between the main circuit region and the scribe region.