Patents by Inventor Hideo Kudo

Hideo Kudo has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20030118772
    Abstract: A film constitution in an optical recording medium includes a light incident side substrate 6 and a light reflecting side substrate 1 cooperatively acting as a base of the medium, and includes, between these substrates, those layers formed by sputtering so as to constitute a laminated structure, which layers include: a phase-change recording layer 4 to be phase-changed between an amorphous phase and a crystal phase by laser light irradiation; a first dielectric layer 5 and a second dielectric layer 3, each having a protective function and an optical adjusting function for the phase-change recording layer 4; a reflecting film layer 2 for reflecting the laser light transmitted through the phase-change recording layer 4; a hardness enhancing layer 7 for enhancing the mechanical strength of the medium; and a protecting layer 8 having a function for reducing thermal damages to the light incident side substrate and an optical adjusting function.
    Type: Application
    Filed: October 7, 2002
    Publication date: June 26, 2003
    Applicant: PIONEER CORPORATION
    Inventors: Yasuo Hosoda, Satoshi Jinno, Ayumi Mitsumori, Hideo Kudo
  • Patent number: 6432837
    Abstract: A method of processing a semiconductor wafer sliced from a monocrystalline ingot comprises at least the steps of chamfering, lapping, etching, mirror-polishing, and cleaning. In the etching step, alkali etching is first performed and then acid etching, preferably reaction-controlled acid etching, is performed. The etching amount of the alkali etching is greater than the etching amount of the acid etching. Alternatively, in the etching step, reaction-controlled acid etching is first performed and then diffusion-controlled acid etching is performed. The etching amount of the reaction-controlled acid etching is greater than the etching amount of the diffusion-controlled acid etching.
    Type: Grant
    Filed: February 7, 2001
    Date of Patent: August 13, 2002
    Assignee: Shin-Etsu Handotai Co., Ltd.
    Inventors: Takashi Nihonmatsu, Seiichi Miyazaki, Masahiko Yoshida, Hideo Kudo, Tadahiro Kato
  • Patent number: 6402594
    Abstract: A polishing method for wafer, comprises the steps of; adhering a wafer to a wafer adhesion part of a holding plate through a wax, and rubbing the wafer with a polishing pad, wherein grooves are formed on the wafer adhesion part and extend to the outside of the wafer adhesion part.
    Type: Grant
    Filed: December 29, 1999
    Date of Patent: June 11, 2002
    Assignee: Shin-Etsu Handotai Co., Ltd.
    Inventors: Daisuke Kobayashi, Tsuyoshi Matsuzaki, Hideo Kudo
  • Patent number: 6346485
    Abstract: A method of processing a semiconductor wafer sliced from a monocrystalline ingot comprises at least the steps of chamfering, lapping, etching, mirror-polishing, and cleaning. In the etching step, alkali etching is first performed and then acid etching, preferably reaction-controlled acid etching, is performed. The etching amount of the alkali etching is greater than the etching amount of the acid etching. Alternatively, in the etching step, reaction-controlled acid etching is first performed and then diffusion-controlled acid etching is performed. The etching amount of the reaction-controlled acid etching is greater than the etching amount of the diffusion-controlled acid etching.
    Type: Grant
    Filed: August 7, 2000
    Date of Patent: February 12, 2002
    Assignee: Shin-Etsu Handotai Co., Ltd.
    Inventors: Takashi Nihonmatsu, Seiichi Miyazaki, Masahiko Yoshida, Hideo Kudo, Tadahiro Kato
  • Publication number: 20010008807
    Abstract: A method of processing a semiconductor wafer sliced from a monocrystalline ingot comprises at least the steps of chamfering, lapping, etching, mirror-polishing, and cleaning. In the etching step, alkali etching is first performed and then acid etching, preferably reaction-controlled acid etching, is performed. The etching amount of the alkali etching is greater than the etching amount of the acid etching. Alternatively, in the etching step, reaction-controlled acid etching is first performed and then diffusion-controlled acid etching is performed. The etching amount of the reaction-controlled acid etching is greater than the etching amount of the diffusion-controlled acid etching.
    Type: Application
    Filed: February 7, 2001
    Publication date: July 19, 2001
    Applicant: SHIN-ETSU HANDOTAI CO., LTD.
    Inventors: Takashi Nihonmatsu, Seiichi Miyazaki, Masahiko Yoshida, Hideo Kudo
  • Patent number: 6239039
    Abstract: A method of processing a semiconductor wafer sliced from a monocrystalline ingot comprises at least the steps of chamfering, lapping, etching, mirror-polishing, and cleaning. In the etching step, alkali etching is first performed and then acid etching, preferably reaction-controlled acid etching, is performed. The etching amount of the alkali etching is greater than the etching amount of the acid etching. Alternatively, in the etching step, reaction-controlled acid etching is first performed and then diffusion-controlled acid etching is performed. The etching amount of the reaction-controlled acid etching is greater than the etching amount of the diffusion-controlled acid etching.
    Type: Grant
    Filed: December 8, 1998
    Date of Patent: May 29, 2001
    Assignee: Shin-Etsu Handotai Co., Ltd.
    Inventors: Takashi Nihonmatsu, Seiichi Miyazaki, Masahiko Yoshida, Hideo Kudo, Tadahiro Kato
  • Patent number: 6110839
    Abstract: A method of purifying an alkaline solution includes dissolving metallic silicon and/or silicon compounds in the alkaline solution and non-ionizing metallic ions in the alkaline solution with reaction products generated when the metallic silicon and/or silicon compounds are dissolved therein. This purifying method is capable of remarkably decreasing metallic ions in the alkaline solution at a low-cost by an easy operation. A method of etching semiconductor wafers includes purifying an alkaline solution by non-ionizing metallic ions in the alkaline solution and etching the semiconductor wafers by using the purified alkaline solution. According to this etching method, the metallic contamination level due to the etching of the semiconductor wafers is greatly decreased, there being neither deterioration in the wafer quality nor deterioration in the characteristic of the semiconductor device.
    Type: Grant
    Filed: August 27, 1996
    Date of Patent: August 29, 2000
    Assignee: Shin-Etsu Handotai Co., Ltd.
    Inventors: Masami Nakano, Isao Uchiyama, Toshio Ajito, Hideo Kudo
  • Patent number: 6077149
    Abstract: In a surface-grinding method for a workpiece, for example a semiconductor wafer, it is possible to correct or improve waviness and bow and to obtain a semiconductor wafer having no thickness dispersion. Besides, wafer processing to higher precision than that conventionally attained is achieved and at the same time simplification of the processing method and thereby reduction of the cost are also achieved. In the present invention, while the workpiece is fixed for supporting at one surface by the fixedly supporting means of a surface-grinding apparatus, the other surface of the workpiece is surface-ground, where the workpiece adheres on the upper surface of a base plate by the aid of adhesive material and the base plate is fixedly supported by the lower surface of itself on the fixedly supporting means.
    Type: Grant
    Filed: October 17, 1997
    Date of Patent: June 20, 2000
    Assignee: Shin-etsu Handotai Co., Ltd.
    Inventors: Sadayuki Ohkuni, Tadahiro Kato, Hideo Kudo
  • Patent number: 6050880
    Abstract: A surface grinding method for a thin-plate workpiece is provided including the steps of (a) roughly surface grinding a first surface of a thin-plate workpiece using a thin-plate workpiece surface grinding device to create a reference plane having no sori or waviness; (b) inverting the thin-plate workpiece, the first surface of which has been roughly surface ground and, with a surface grinding device having a hard chucking plate, chucking the first surface to the hard chucking plate to roughly surface grind a second surface of the thin-plate workpiece; (c) chucking to the hard chucking plate the first surface of the thin-plate workpiece, the second surface of which has been roughly surface ground with the surface grinding device having the hard chucking plate to further finely surface grind the second surface of the thin-plate workpiece; and (d) inverting the thin-plate workpiece, the second surface of which has been finely surface ground and, with the surface grinding device having the hard chucking plate, ch
    Type: Grant
    Filed: December 22, 1997
    Date of Patent: April 18, 2000
    Assignee: Shin-Etsu Handotai Co., Ltd.
    Inventors: Tadahiro Kato, Sadayuki Okuni, Hideo Kudo, Hiroshi Tomioka
  • Patent number: 5951374
    Abstract: A method of polishing semiconductor wafers includes a double side primary polishing step and a single side secondary polishing step using a single side polishing machine with a wafer holder including a template so bonded on a carrier plate as having one or more wafer receiving holes in which backing pads are disposed respectively for holding the back sides of the respective wafers fittingly received therein. This method makes it to possible to hold a plurality of wafers at one time due to batch processing to thereby improve the productivity, and decrease extremely the generation of the defective dimples in the front side of the wafer. Compared with conventional single side polishing, the flatness level of the wafer polished with the double side polishing machine in this method is improved.
    Type: Grant
    Filed: January 28, 1997
    Date of Patent: September 14, 1999
    Assignee: Shin-Etsu Handotai Co., Ltd.
    Inventors: Tadahiro Kato, Hisashi Masumura, Masami Nakano, Hideo Kudo
  • Patent number: 5942445
    Abstract: According to the invention, the flatness and quality can be improved while simplifying the process even when large size wafers of 200 to 300 mm or above are processed. Basic steps involved are a slicing step E for obtaining thin disc-shape wafers by slicing, a chamfering step F for chamfering the sliced wafers, a flattening step G for flattening the chamfered wafers, an alkali etching step H for removing process damage layers from the flattened wafers, and a double-side polishing step K of simultaneously polishing the two sides of the etched wafers. If necessary, a plasma etching step is used in lieu of the flattening and etching steps G and H respectively.
    Type: Grant
    Filed: March 25, 1997
    Date of Patent: August 24, 1999
    Assignee: Shin-Etsu Handotai Co., Ltd.
    Inventors: Tadahiro Kato, Hisashi Masumura, Sadayuki Okuni, Hideo Kudo
  • Patent number: 5914053
    Abstract: In double-side polishing of semiconductor wafers, not only the two main surfaces but also the surface of the edge portion can be polished in one operation with cost reduction and freedom from contamination. An apparatus with twin polishing turn tables is used in the double-side polishing and the inner peripheral edge of each carrier hole formed in a wafer carrier is profiled such that the sectional profile of the inner peripheral edge is substantially the copy of the edge of the wafer placed in the hole.
    Type: Grant
    Filed: November 14, 1996
    Date of Patent: June 22, 1999
    Assignee: Shin-Etsu Handotai Co., Ltd.
    Inventors: Hisashi Masumura, Kiyoshi Suzuki, Hideo Kudo
  • Patent number: 5891353
    Abstract: A semiconductor wafer polishing agent contains mainly a silica containing polishing agent and is added with a polyolefin type fine particle material. The novel semiconductor wafer polishing agent is capable of low brightness polishing to the back face of the wafer, sensor detection of the front and back faces of the wafer, and suppression of dust to be generated by chipping of the back face of the wafer, thereby to increase the yield of semiconductor devices. A polishing method using the polishing agent and a novel semiconductor wafer having a back face with an unconventional surface shape are also disclosed.
    Type: Grant
    Filed: August 21, 1997
    Date of Patent: April 6, 1999
    Assignee: Shin-Etsu Handotai Co, Ltd.
    Inventors: Hisashi Masumura, Kiyoshi Suzuki, Hideo Kudo, Teruaki Fukami
  • Patent number: 5866226
    Abstract: A semiconductor wafer polishing agent contains mainly a silica containing polishing agent and is added with a polyolefin type fine particle material. The novel semiconductor wafer polishing agent is capable of low brightness polishing to the back face of the wafer, sensor detection of the front and back faces of the wafer, and suppression of dust to be generated by chipping of the back face of the wafer, thereby to increase the yield of semiconductor devices. A polishing method using the polishing agent and a novel semiconductor wafer having a back face with an unconventional surface shape are also disclosed.
    Type: Grant
    Filed: June 20, 1996
    Date of Patent: February 2, 1999
    Assignee: Shin-Etsu Handotai Co., Ltd.
    Inventors: Hisashi Masumura, Kiyoshi Suzuki, Hideo Kudo, Teruaki Fukami
  • Patent number: 5827779
    Abstract: A method of manufacturing semiconductor mirror wafers includes a double side primary mirror polishing step and a single side final mirror polishing step. The method having the double side mirror polishing step is capable of higher flatness level wafer processing, suppression of fine dust or particles, thereby to increase the yield of semiconductor devices, higher productivity due to simplification of processes, higher quality processing with lower manufacturing cost than conventional methods.
    Type: Grant
    Filed: July 19, 1996
    Date of Patent: October 27, 1998
    Assignee: Shin-Etsu Handotai Co. Ltd.
    Inventors: Hisashi Masumura, Kiyoshi Suzuki, Hideo Kudo
  • Patent number: 5827395
    Abstract: A polishing pad composed of a rigid polyurethane added with CaCO.sub.3 particles is able to provide polished wafers having a surface roughness which is comparable to that attained by the conventional final polishing process. Even when polishing is achieved under a high load condition to improve the productivity, the polished wafers are free from deformation, such as concaving, and have an excellent flatness.
    Type: Grant
    Filed: May 31, 1995
    Date of Patent: October 27, 1998
    Assignee: Shin-Etsu Handotai Co., Ltd.
    Inventors: Hisashi Masumura, Kiyoshi Suzuki, Hideo Kudo
  • Patent number: 5821167
    Abstract: A method of manufacturing semiconductor mirror wafers includes a double side primary mirror polishing step, a back side low brightness polishing step and a front side final mirror polishing step, wherein a silica containing polishing agent is used together with a polyolefin type fine particle material for the back side low brightness polishing. The method is capable of low brightness polishing of the back side, sensor detection of the front and back sides, suppression of generation of fine dust or particles from back side, thereby to increase the yield of semiconductor devices, manufacturing mirror wafers with higher flatness level, and higher productivity due to simplification of processes.
    Type: Grant
    Filed: December 26, 1996
    Date of Patent: October 13, 1998
    Assignee: Shin-Etsu Handotai Co., Ltd.
    Inventors: Teruaki Fukami, Hisashi Masumura, Kiyoshi Suzuki, Hideo Kudo
  • Patent number: 5800725
    Abstract: A method of manufacturing semiconductor wafers includes a double side primary polishing step, a back side etching step and a single side mirror polishing step. This method is capable of easy sensor detection of the front and back sides of the wafer, wafer processing of higher flatness level by forming etched rough surface at the back side of the double side polished wafer and setting up of wafer manufacturing process including a double side polishing step.
    Type: Grant
    Filed: January 28, 1997
    Date of Patent: September 1, 1998
    Assignee: Shin-Etsu Handotai Co., Ltd.
    Inventors: Tadahiro Kato, Hisashi Masumura, Hideo Kudo
  • Patent number: 5790252
    Abstract: The invention seeks to permit evaluation of edge portion of like inclined surfaces of wafer with high accuracy without the conventional destruction process based on the selective etching process but with the contact-free, non-destructive and high accuracy optical acoustical process. To this end, the invention features determination of residual damages as crystal damages caused to wafer edge in an optical acoustical process, which comprises the steps of causing a measurement probe to face each of three exciting laser beam irradiation points on upper and lower inclined surfaces and at an accurate end of an edge portion of a semiconductor wafer, and determining a thermal response induced by the exciting laser beam by a laser interference process.
    Type: Grant
    Filed: September 27, 1996
    Date of Patent: August 4, 1998
    Assignee: Shin-Etsu Handotai Co., Ltd.
    Inventors: Hisashi Masumura, Hideo Kudo, Shingo Sumie, Hidetoshi Tsunaki, Yuji Hirao, Noritaka Morioka
  • Patent number: 5768243
    Abstract: An optical recording medium which is constructed in a manner such that a plurality of recording areas in which an information signal is recorded along vortical spiral tracks are arranged in a ring shape on a recording surface and a vortex direction of the spiral track of the outside recording area among the plurality of recording areas differs from that of the spiral track of the inside recording area. When the information signal is recorded to the recording medium, the first writing device executes the writing operation from the outer rim side toward the inner rim side of the spiral track of the outside recording area and the second writing device executes the writing operation from the inner rim side toward the outer rim side of the spiral track of the outside recording area.
    Type: Grant
    Filed: March 26, 1997
    Date of Patent: June 16, 1998
    Assignee: Pioneer Electronic Corporation
    Inventors: Hideo Kudo, Yoshimi Tomita