Abstract: A semiconductor device includes a system bus, a plurality of Central Processing Unit (CPU) cores each connected to the system bus, including a scan chain, and being assigned one or more tasks and configured to perform one of the tasks in a normal operation state, and a diagnostic test circuit connected to the system bus and capable of communicating with the plurality of the CPU cores, and configured to perform a scan test for the plurality of the CPU cores by using the scan chain. The plurality of the CPU cores outputs a test start instruction signal to the diagnostic test circuit, when the test start instruction signal is output from one of the plurality of the CPU cores, the diagnostic test circuit performs a scan test for the one of the plurality of the CPU cores in accordance with the test start instruction signal.

Abstract: A data processing apparatus includes a memory, a processor which outputs write data when making a write request to the memory, and which inputs read data when making a read request to the memory, a parity generating circuit which generates a parity comprising a plurality of parity bits from the write data, the parity being written with the write data into the memory, and a parity check circuit which is coupled between the memory and the processor, and which detects a presence or absence of an error of one bit or two bits in the read data and the parity read from the memory, wherein the parity generating circuit generates the parity so that at least one of a first write data bit and a second write data bit included in the write data contributes to generation of at least two parity bits.

Abstract: A data processing apparatus includes a memory, a processor which outputs write data when making a write request to the memory, and which inputs read data when making a read request to the memory, a parity generating circuit which generates a parity comprising a plurality of parity bits from the write data, the parity being written with the write data into the memory, and a parity check circuit which is coupled between the memory and the processor, and which detects a presence or absence of an error of one bit or two bits in the read data and the parity read from the memory, wherein the parity generating circuit generates the parity so that at least one of a first write data bit and a second write data bit included in the write data contributes to generation of at least two parity bits.

Abstract: A data reception device includes: an equalizer circuit that shapes a waveform of an input signal according to a set gain value; a CDR circuit which recovers a plurality of clock signals having different phases in one cycle from the input signal after being subjected to the waveform shaping performed by the equalizer circuit; an oversampler which performs sampling of the waveform-shaped input signal in synchronization with the plurality of clock signals and recovers a plurality of input data from the waveform-shaped input signal; and a calibration control unit which determines whether the oversampler correctly recovers the input data based on a result of the sampling performed by the oversampler, and generates a control signal to set the gain value of the equalizer circuit based on a determination result when it is determined that the input data is not correctly recovered.

Abstract: A data processing apparatus includes a memory, a processor which outputs write data when making a write request to the memory, and which inputs read data when making a read request to the memory, a first circuit which is coupled between the memory and the processor, and which includes a parity generating circuit generating a parity comprising a plurality of parity bits from the write data, the parity being written with the write data into the memory, and a second circuit which is coupled between the memory and the processor, and which includes a parity check circuit detecting a presence or an absence of an error of one-bit or two-bits in the read data and the parity read from the memory.

Abstract: A semiconductor device includes a system bus, a plurality of Central Processing Unit (CPU) cores each connected to the system bus, including a scan chain, and being assigned one or more tasks and configured to perform one of the tasks in a normal operation state, and a diagnostic test circuit connected to the system bus and capable of communicating with the plurality of the CPU cores, and configured to perform a scan test for the plurality of the CPU cores by using the scan chain. The plurality of the CPU cores outputs a test start instruction signal to the diagnostic test circuit, when the test start instruction signal is output from one of the plurality of the CPU cores, the diagnostic test circuit performs a scan test for the one of the plurality of the CPU cores in accordance with the test start instruction signal.

Abstract: A data reception device includes: an equalizer circuit that shapes a waveform of an input signal according to a set gain value; a CDR circuit which recovers a plurality of clock signals having different phases in one cycle from the input signal after being subjected to the waveform shaping performed by the equalizer circuit; an oversampler which performs sampling of the waveform-shaped input signal in synchronization with the plurality of clock signals and recovers a plurality of input data from the waveform-shaped input signal; and a calibration control unit which determines whether the oversampler correctly recovers the input data based on a result of the sampling performed by the oversampler, and generates a control signal to set the gain value of the equalizer circuit based on a determination result when it is determined that the input data is not correctly recovered.

Abstract: Deterioration in operation performance due to a fault diagnosis is prevented. A semiconductor device 90 according to the present invention includes a plurality of CPU cores 91 to 94 each including a scan chain, and a diagnostic test circuit 95 that performs a scan test for the plurality of CPU cores 91 to 94 by using the scan chain of the CPU core. The diagnostic test circuit 95 performs a scan test for each of the plurality of CPU cores 91 to 94 in a predetermined order on a periodic basis so that execution time periods of the scan tests do not overlap each other.

Abstract: A data processing apparatus includes a memory, a processor which outputs write data when making a write request to the memory, and which inputs read data when making a read request to the memory, a first circuit which is coupled between the memory and the processor, and which includes a parity generating circuit generating a parity comprising a plurality of parity bits from the write data, the parity being written with the write data into the memory, and a second circuit which is coupled between the memory and the processor, and which includes a parity check circuit detecting a presence or an absence of an error of one-bit or two-bits in the read data and the parity read from the memory.

Abstract: A data processing apparatus including a processor and a memory has a parity/ECC encoder circuit and a parity/ECC decoder circuit. The parity/ECC encoder circuit is disposed in a signal path for writing data to the memory, includes a parity generating circuit for generating a parity of a plurality of bits from data to be written, and writes the generated parity together with the data into the memory. The parity/ECC decoder circuit is disposed in a signal path for reading data from the memory and includes a parity check unit. The parity generating circuit is configured so that each of a plurality of bits configuring the data contributes to generation of a parity of at least two bits. Consequently, the parity check unit can detect a two-bit error at high speed.

Abstract: Deterioration in operation performance due to a fault diagnosis is prevented. A semiconductor device 90 according to the present invention includes a plurality of CPU cores 91 to 94 each including a scan chain, and a diagnostic test circuit 95 that performs a scan test for the plurality of CPU cores 91 to 94 by using the scan chain of the CPU core. The diagnostic test circuit 95 performs a scan test for each of the plurality of CPU cores 91 to 94 in a predetermined order on a periodic basis so that execution time periods of the scan tests do not overlap each other.

Abstract: A data processing apparatus including a processor and a memory has a parity/ECC encoder circuit and a parity/ECC decoder circuit. The parity/ECC encoder circuit is disposed in a signal path for writing data to the memory, includes a parity generating circuit for generating a parity of a plurality of bits from data to be written, and writes the generated parity together with the data into the memory. The parity/ECC decoder circuit is disposed in a signal path for reading data from the memory and includes a parity check unit. The parity generating circuit is configured so that each of a plurality of bits configuring the data contributes to generation of a parity of at least two bits. Consequently, the parity check unit can detect a two-bit error at high speed.

Abstract: An optical sheet having both a light condensing function and a light diffusing function in a single sheet is to be provided. When a transparent support (18) on which a curable resin coat layer (38) is formed is wound around a zigzag-faced roller (32) on which the reversed pattern of convex-concave patterns is formed to transfer the reversed pattern of the zigzag-faced roller (32) to the resin coat layer (38), gas is blown from a gas jet nozzle (50), immediately before winding the transparent support (18) around the zigzag-faced roller (32), into a gap between the resin coat layer (38) and the surface of the zigzag-faced roller.

Abstract: An information device packaged in one package includes a main function unit and an interface function unit. The main function unit includes a main processing circuit for executing signal processing related to a main function in the information device and a first microcomputer for controlling the main processing circuit by executing a first firmware program. The interface function unit includes an interface function unit including a first interface circuit for receiving data from an exterior device located outside of the information device to provide to the main function unit, a second interface circuit for performing an authentication operation with the exterior device, a second microcomputer for controlling the first interface circuit, and a memory for storing a second firmware program for controlling the first interface circuit.

Abstract: The present invention provides an optical functional sheet and a display device that are capable of keeping a given degree or more of front luminance and are capable of substantially reducing brightness nonuniformity. To this end, the optical functional sheet has a base 3, and prisms 4 arranged in a lattice pattern on at least one surface 3a of the base 3, wherein each of the prisms 4 has two bottoms L1 parallel to a first direction D1, two first inclined surfaces S1 that are inclined so as to face each other, two bottoms L2 parallel to a second direction D2 that is substantially perpendicular to the first direction D1, and two second inclined surfaces S2 that are inclined so as to face each other, and the area Ss2 of one of the second inclined surfaces S2 to the sum S2s1 of the areas of the two first inclined surfaces S1, or the area Ss1 of one of the first inclined surfaces S1 to the sum S2s2 of the areas of the two second inclined surfaces S2 is more than 0.5 times to 2.5 times or less.

Abstract: According to the present invention, it is possible to easily manufacture a molded plate of a desired size by laminating an unnecessary, inexpensive resin not used as a product in the width direction of a molded plate and simply separating the unnecessary resin after forming the molded plate. Consequently, it is possible to skip a step of cutting the molded plate in the machine direction thereof. Further, it is also possible to skip a polishing step since the cut surfaces of the molded plate in the machine direction thereof can be smoothed. Still further, by arranging a plurality of resins for disposal, it is possible to effectively use the resins when yielding multiple molded plates from one resin sheet.

Abstract: An information device packaged in one package includes a main function unit and an interface function unit. The main function unit includes a main processing circuit for executing signal processing related to a main function in the information device and a first microcomputer for controlling the main processing circuit by executing a first firmware program. The interface function unit includes an interface function unit including a first interface circuit for receiving data from an exterior device located outside of the information device to provide to the main function unit, a second interface circuit for performing an authentication operation with the exterior device, a second microcomputer for controlling the first interface circuit, and a memory for storing a second firmware program for controlling the first interface circuit.

Abstract: An information device includes a main processing circuit for executing signal processing related to a main function in the information device, a main microcomputer for controlling the main processing circuit, a receiver circuit for interfacing with the outside of the information device, and an interface microcomputer for controlling the receiver circuit, the interface microcomputer being provided separately from the main microcomputer.

Abstract: A method according to the invention comprises an extruding step of extruding molten resin from a die in a belt shape, a molding/cooling step of cooling and solidifying the extruded resin sheet while molding the same in uneven thickness by nipping the same between a mold roller and a nip roller, and a slow cooling step of slowly cooling the resin sheet peeled off the mold roller, and at least the former part of the slow cooling step has a substep of slowly cooling the resin sheet while holding the resin sheet in the original warp-free uneven thickness shape while so applying an external force to the resin sheet as not to obstruct the carriage of the resin sheet.

Abstract: A backlight unit, comprising plural linear light sources, and an optical functional sheet, wherein a prism structure having plural prisms is formed on at least one surface of the optical functional sheet, and the values of (Hn?1+Hn)/(An?An?1) are approximately equivalent, wherein, in a brightness distribution graph that expresses a brightness distribution in the optical functional sheet, A1 is a peak site and H1 is a peak height of a first virtual image, A2 is a peak site and H2 is a peak height of a second virtual image adjacent to the first virtual image, . . . , An is a peak site and Hn is a peak height of (n)th virtual image adjacent to (n?1)th virtual image, and these virtual images are derived from the plural linear light sources.