Abstract: A data recovery circuit includes a phase locked loop circuit that includes a phase comparator, a VCO, and a 1/N frequency divider. A sampling reference clock CLK0 multiplied in frequency with respect to an input clock CLK with a factor of 7/4 is generated. Data that corresponds to three periods of the sampling reference clock CLK0 are held in a shift register by taking four bits as the unit. On the other hand, bits output as parallel data from data in the shift register are determined based on a count in a counter that counts seven periods of the sampling reference clock CLK0.

Abstract: A synchronous clock phase control circuit includes a T/8 step phase clock generation unit, a phase selection unit, and four synchronous clock generation units. The T/8 step phase clock generation unit generates eight clocks previously delayed in phase by T/8 from an input clock. The phase selection unit selects four control clocks from the eight clocks generated by the phase clock generation unit based on four phase control signals, respectively. The four synchronous clock generation units synchronize the selected clocks with an externally input trigger signal TR using the input clock as a reference, and output the selected clocks when synchronization is established, respectively.

Abstract: On a semiconductor chip, ends of a plurality of resistive elements of a pull-up resistor unit disposed in parallel to each other are connected to a power source, other ends of the resistive elements are connected to a line connecting a signal input terminal and a receiving end device disposed on the semiconductor chip, and the line is connected to the ground through an external resistor disposed on the outside of the semiconductor chip. A current flows from the power source to the ground, and a node voltage depending on a resistance value of the external resistor and a composite resistance of the pull-up resistor unit is applied to a node between the line and the external resistor. The composite resistance of the pull-up resistor unit functioning as a termination resistor is corrected to an expected value according to the node voltage.

Abstract: The present invention provides a method of producing a pattern member at high productivity and low cost. In the method of the present invention, inks of plural colors are applied on a substrate and dried to produce several kinds of single color films having color ink layers of plural colors formed on the surface, then, the single color film of R color is overlapped on the substrate, and the overlapped substrate and single color film are pressed by a pressing member having a convex portion of given pattern formed on the surface, to transfer parts corresponding to the pattern of the convex portion of the color ink layer to the substrate. The above-described operation is repeated at frequency corresponding to plural colors to form a multi-color pattern composed of color ink layers of plural colors of given pattern on the substrate.

Abstract: A first differential signal received at an input terminal is input to non-inversion terminals of a first comparator and a receiving end device. A second differential signal lower than the first differential signal is received at another input terminal and is input to inversion terminals of a second comparator and the receiving end device. A first reference voltage higher than the first differential signal is applied to an inversion terminal of the first comparator, and a second reference voltage lower than the second differential signal is applied to a non-inversion terminal of the second comparator. When one input terminal is open-circuited or short-circuited, a voltage higher than the first reference voltage or a voltage lower than the second reference voltage is applied to the non-inversion terminal of the first comparator or the inversion terminal of the second comparator.

Abstract: On a semiconductor chip, ends of a plurality of resistive elements of a pull-up resistor unit disposed in parallel to each other are connected to a power source, other ends of the resistive elements are connected to a line connecting a signal input terminal and a receiving end device disposed on the semiconductor chip, and the line is connected to the ground through an external resistor disposed on the outside of the semiconductor chip. A current flows from the power source to the ground, and a node voltage depending on a resistance value of the external resistor and a composite resistance of the pull-up resistor unit is applied to a node between the line and the external resistor. The composite resistance of the pull-up resistor unit functioning as a termination resistor is corrected to an expected value according to the node voltage.

Abstract: An impedance adjustment circuit achieves impedance matching between a terminal resistor in a reception-side semiconductor device and a transmission line. A reference resistor has a first resistance proportional to characteristic impedance of the transmission line. This reference resistor is external to the reception-side semiconductor device. Furthermore, the terminal resistor includes a resistor having a second resistance and an ON resistance of an MOS transistor. The resistance of the terminal resistor is adjusted by referring to the reference resistor.

Abstract: Resistance elements of a differential circuit is formed of a plurality of transistors and transistors which are biased into a linear region deeper than those of other transistors and have a small transistor size are provided on a side of output point of the differential circuit, to thereby reduce a parasitic capacitance as viewed from the output point.

Abstract: The impedance adjustment circuit achieves impedance matching between a terminal resister provided in a reception-side semiconductor device and a transmission line. There is provided a reference resistor having a first resistance which is in proportion to an impedance of the transmission line. This reference resistor provided externally to the reception-side semiconductor device. Furthermore, the terminal resistor is constituted by a resistor having a second resistance and an ON resistor of a MOS transistor. The resistance of the terminal resistor is adjusted by referring to the reference resistor.

Abstract: A differential output circuit is composed of a constant-current circuit section having a reference voltage circuit, an amplification circuit, a resistance, an N-channel MOS transistor and a P-channel MOS transistor; a mirror circuit section having three P-channel MOS transistors; a data transmission switch circuit section having a data input terminal, an inverter circuit, positive and negative output terminals, and two N-channel MOS transistors; and an offset level adjusting circuit section having a resistance.

Abstract: A differential output circuit is composed of a constant-current circuit section having a reference voltage circuit, an amplification circuit, a resistance, an N-channel MOS transistor and a P-channel MOS transistor; a mirror circuit section having three P-channel MOS transistors; a data transmission switch circuit section having a data input terminal, an inverter circuit, positive and negative output terminals, and two N-channel MOS transistors; and an offset level adjusting circuit section having a resistance.

Abstract: A skew adjusting circuit can carry out optimum correction of skew by automatically reading skew amounts of transmission paths with a receiving-side IC, without setting particular skew amounts externally. The skew adjusting circuit includes delay generating circuits, a plurality sets of flip-flops, decoders and selectors. Each delay generating circuit is provided to one of channels, and includes delay elements, each of which has a same delay amount. Each set of the flip-flops is provided to one of the delay generating circuits except for a first delay generating circuit corresponding to a reference channel signal. The flip-flops of each set receive an output of a final delay element of the first delay generating circuit as a clock signal, and receive tap outputs of the associated one of the delay generating circuits. Each decoder receives outputs of the flip-flops of one of the sets of flip-flops.

Abstract: There is described a charge pump circuit capable of minimizing an offset in a phase difference at the time of zero output current, which would otherwise be caused by variations in elements stemming from variations in a manufacturing process. When a first input signal becomes low, a first MOS transistor is brought into conduction, and an electric current "I1" specified by a second MOS transistor flows to an output node as a charge current. When a second input signal becomes low, a third MOS transistor is brought into conduction, and an electric current "I2" specified by a fourth MOS transistor flows to a current mirror circuit. The current mirror circuit withdraws an electric current "I6"--which is the same as that of the electric current "I2"--from the output node as a discharge current. When the charge or discharge current flows to the output node, there is output an electric current of zero. If there is only the charge current, the charge current flows from the output node.

Abstract: An output circuit is constructed such that a load capacitor is not charged by an external power supply but by a first charge storage element within a semiconductor chip that is charged before the load capacitor. The charge stored in the load capacitor is released not directly to the ground but to a second charge storage element within the semiconductor chip and discharged before discharging of the load capacitor.

Abstract: A pulse-width modulation signal generator having a pre-phase converter which includes N pre-delay circuits connected in cascade, and N main phase converters each of which includes M main delay circuits, where N and M are natural numbers greater than one, and N>M. The output of each of the N pre-phase circuits is supplied to one of the N main phase converters to generate phase converted clock signals used for generating a pulse-width modulation signal.

Abstract: In a production line for microcapsules, which is provided with an emulsifying machine, an emulsion or microcapsules are automatically sampled on a on-line basis from a portion of a process pipeline, which portion is located downstream of the emulsifying machine. The obtained sample is fed into a particle diameter measuring device, and the particle diameters of the microcapsules in the sample are automatically measured by the particle diameter measuring device. A calculation is made by a process computer in order to find the difference between the measured values of the particle diameters and a desired particle diameter. The value of a rotation speed of the emulsifying machine, which value yields the desired particle diameter, is calculated in accordance with the relationship between the rotation speed of the emulsifying machine and the mean particle diameter, the relationship having been inputted previously.

Abstract: A process for the preparation of microcapsules having a wall membrane made of a polyurethane urea resin, which includes steps of mixing an oily solution and an aqueous solution, passing the resulting mixed solution through a clearance between an inner cylinder and an outer cylinder which are rotated relative to each other to form an oil-in-water type emulsion, and then forming a wall membrane on droplets of the resulting emulsion. In a preferred embodiment, the clearance between the inner cylinder and the outer cylinder is preferably in the range of 0.05 to 5 mm, more preferably 0.1 to 2 mm. The retention time of the emulsion in the clearance portion is in the range of 0.02 seconds or more, preferably 0.2 seconds or more. The inner and outer cylinders are in the form of column, optionally conical in part thereof.

Abstract: A process for producing microcapsules that have a sufficiently broad particle size distribution to be suitable for use in a pressure measuring films, which process is improved in that it eliminates the need to perform blending and filtering operations while reducing the possible loss in capsule solutions or films or operating efficiency of the capsule applicator. A disperse phase is poured into a disperse medium as the latter is stirred in a preliminary emulsification tank, thereby forming a primary emulsion. The primary emulsion is forced into cylindrical continuous emulsification equipment by means of a metering pump. An emulsion having a broad particle size distribution is produced by lowering stepwise the rotational speed of the inner cylinder of the continuous emulsification equipment in accordance with the following schedule: 3 min and 15 sec at 2900 rpm, 4 min and 15 sec at 2700 rpm, 4 min and 15 sec at 2300 rpm, and 3 min and 15 sec at 2100 rpm.

Abstract: It is an object to accurately obtain the period of the horizontal synchronizing signal in the video signal. The number of internal pulses are measured in a predetermined measurement period defined by the horizontal synchronizing signal. It is assumed that the periods of the horizontal synchronizing signal and the internal pulse are denoted as T.sub.H and T.sub.S, and the measurement period is defined by one period of a divided signal NS which is obtained by N-dividing the horizontal synchronizing signal. In this case, the length of the measurement period is N.multidot.T.sub.H. The period of the horizontal synchronizing signal is obtained when the internal pulse is activated K times in the measurement period. After the measurement period is started, the divided signal NS transits between the Kth activation of the internal pulse and the (K+1)th activation, and the measurement period is ended. Accordingly, there is the relation of T.sub.S .multidot.K<N.multidot.T.sub.H <T.sub.S .multidot.(K+1). The error .

Abstract: A method for manufacturing microcapsules which prevents capsule particles from adhering to the inner wall surfaces of a wall-film-forming reactor device, thereby to eliminate the possibility that qualities of the microcapsule, such as the heat resisting, solvent resisting and other properties thereof, are deteriorated, and to eliminate the need for an operation to clean substances adhered to the inner wall surfaces of the wall-film-forming reactor device, and therefore, which is able to manufacture microcapsules at a high production efficiency. An emulsified solution is injected into a wall-film-forming reactor device from the lower portion thereof by an emulsified solution feed pump. After completion of a given time of a wall-film-forming reaction in the wall-film-forming reactor device, the emulsified solution is discharged from an overflow outlet formed in the upper portion of the device, and is then cooled by a heat exchanger.