Patents by Inventor Hideo Nakaya

Hideo Nakaya has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7240128
    Abstract: An integrated processing box performs processing commonly to a plurality of input devices, a plurality of output devices, or a plurality of storage devices. For example, the integrated processing box performs noise reduction processing on data received from an input device or a storage device or data supplied to an output device or the storage device. The integrated processing box also performs processing, for example, temporal/spatial processing or grayscale processing, variably to each type of input device, each type of output device, or each type of storage device. Accordingly, if the input device is, for example, a video camera, the video camera is formed only by a CCD, a sample-and-hold circuit for sampling and holding the output from the CCD, an AGC circuit for adjusting the gain of the output from the sample-and-hold circuit, and an A/D conversion circuit for converting the analog output of the AGC circuit into a digital output.
    Type: Grant
    Filed: December 15, 2005
    Date of Patent: July 3, 2007
    Assignee: Sony Corporation
    Inventors: Tetsujiro Kondo, Hideo Nakaya
  • Patent number: 7206452
    Abstract: JPEG encoded data are entropy-decoded to quantized DCT coefficients which are sent to a prediction tap extraction circuit (41) and to a class tap extraction circuit (42). The prediction tap extraction circuit (41) and the class tap extraction circuit (42) extract what is needed from the quantized DCT coefficients to form prediction taps and class taps. A classification circuit (43) effects classification based on the class taps. A coefficient table storage unit (44) sends tap coefficients corresponding to the classes resulting from the classification to a sum of products circuit (45), which sum of products circuit (45) then effects linear predictive calculations, using the tap coefficients and the class taps, to generate decoded picture data.
    Type: Grant
    Filed: February 7, 2006
    Date of Patent: April 17, 2007
    Assignee: Sony Corporation
    Inventors: Tetsujiro Kondo, Toshihiko Hamamatsu, Hideo Nakaya, Takeharu Nishikata, Hideki Ohtsuka, Takeshi Kunihiro, Takafumi Morifuji, Masashi Uchida
  • Publication number: 20070076104
    Abstract: An image signal generated by a CCD image sensor is processed by the block-generating section 28 provided in an image-signal processing section 25. A class tap and a prediction tap are thereby extracted. The class tap is output to an ADRC process section 29, and the prediction tap is output to an adaptation process section 31. The ADRC process section 29 performs an ADRC process on the input image signal, generating characteristic data. A classification process section 30 generates a class code corresponding to the characteristic data thus generated and supplies the same to an adaptation process section 31. The adaptation process section 31 reads, from a coefficient memory 32, the set of prediction coefficients which corresponds to the class code. The set of prediction coefficients and the prediction tap are applied, thereby generating all color signals, i.e., R, G and B signals, at the positions of the pixels which are to be processed.
    Type: Application
    Filed: November 1, 2006
    Publication date: April 5, 2007
    Inventors: Tetsujiro Kondo, Hideo Nakaya, Takashi Sawao
  • Publication number: 20070058873
    Abstract: JPEG encoded data are entropy-decoded to quantized DCT coefficients which are sent to a prediction tap extraction circuit (41) and to a class tap extraction circuit (42). The prediction tap extraction circuit (41) and the class tap extraction circuit (42) extract what is needed from the quantized DCT coefficients to form prediction taps and class taps. A classification circuit (43) effects classification based on the class taps. A coefficient table storage unit (44) sends tap coefficients corresponding to the classes resulting from the classification to a sum of products circuit (45), which sum of products circuit (45) then effects linear predictive calculations, using the tap coefficients and the class taps, to generate decoded picture data.
    Type: Application
    Filed: October 20, 2006
    Publication date: March 15, 2007
    Inventors: Tetsujiro Kondo, Toshihiko Hamamatsu, Hideo Nakaya, Takeharu Nishikata, Hideki Ohtsuka, Takeshi Kunihiro, Takafumi Morifuji, Masashi Uchida
  • Publication number: 20070041665
    Abstract: A data processing apparatus is capable of executing a plurality of signal processes. The data processing apparatus switches processes of a pre-processing portion, a data processing portion, and a post-processing portion with a control signal supplied from a function controlling portion corresponding to a command supplied from the outside. Thus, the data processing apparatus executes for example processes for increasing the resolution, generating a picture dedicated for a right eye and a picture dedicated for a left-eye, generating a luminance signal and color difference signals, changing the aspect ratio, generating pictures having difference resolutions, and converting the frame rate for input data corresponding to a request and outputs picture data generated as the processed result to an external device (for example, a displaying device and a record and reproduction device).
    Type: Application
    Filed: October 27, 2006
    Publication date: February 22, 2007
    Inventors: Tetsujiro Kondo, Hideo Nakaya
  • Publication number: 20070036449
    Abstract: JPEG encoded data are entropy-decoded to quantized DCT coefficients which are sent to a prediction tap extraction circuit (41) and to a class tap extraction circuit (42). The prediction tap extraction circuit (41) and the class tap extraction circuit (42) extract what is needed from the quantized DCT coefficients to form prediction taps and class taps. A classification circuit (43) effects classification based on the class taps. A coefficient table storage unit (44) sends tap coefficients corresponding to the classes resulting from the classification to a sum of products circuit (45), which sum of products circuit (45) then effects linear predictive calculations, using the tap coefficients and the class taps, to generate decoded picture data.
    Type: Application
    Filed: October 20, 2006
    Publication date: February 15, 2007
    Inventors: Tetsujiro Kondo, Toshihiko Hamamatsu, Hideo Nakaya, Takeharu Nishikata, Hideki Ohtsuka, Takeshi Kunihiro, Takafumi Morifuji, Masashi Uchida
  • Publication number: 20070036450
    Abstract: JPEG encoded data are entropy-decoded to quantized DCT coefficients which are sent to a prediction tap extraction circuit (41) and to a class tap extraction circuit (42). The prediction tap extraction circuit (41) and the class tap extraction circuit (42) extract what is needed from the quantized DCT coefficients to form prediction taps and class taps. A classification circuit (43) effects classification based on the class taps. A coefficient table storage unit (44) sends tap coefficients corresponding to the classes resulting from the classification to a sum of products circuit (45), which sum of products circuit (45) then effects linear predictive calculations, using the tap coefficients and the class taps, to generate decoded picture data.
    Type: Application
    Filed: October 20, 2006
    Publication date: February 15, 2007
    Inventors: Tetsujiro Kondo, Toshihiko Hamamatsu, Hideo Nakaya, Takeharu Nishikata, Hideki Ohtsuka, Takeshi Kunihiro, Takafumi Morifuji, Masashi Uchida
  • Patent number: 7174051
    Abstract: A data processing apparatus is capable of executing a plurality of signal processes. The data processing apparatus switches processes of a pre-processing portion, a data processing portion, and a post-processing portion with a control signal supplied from a function controlling portion corresponding to a command supplied from the outside. Thus, the data processing apparatus executes for example processes for increasing the resolution, generating a picture dedicated for a right eye and a picture dedicated for a left eye, generating a luminance signal and color difference signals, changing the aspect ratio, generating pictures having difference resolutions, and converting the frame rate for input data corresponding to a request and outputs picture data generated as the processed result to an external device (for example, a displaying device and a record and reproduction device).
    Type: Grant
    Filed: May 29, 2001
    Date of Patent: February 6, 2007
    Assignee: Sony Corporation
    Inventors: Tetsujiro Kondo, Hideo Nakaya
  • Patent number: 7136942
    Abstract: An integrated processing box performs processing commonly to a plurality of input devices, a plurality of output devices, or a plurality of storage devices. For example, the integrated processing box performs noise reduction processing on data received from an input device or a storage device or data supplied to an output device or the storage device. The integrated processing box also performs processing, for example, temporal/spatial processing or grayscale processing, variably to each type of input device, each type of output device, or each type of storage device. Accordingly, if the input device is, for example, a video camera, the video camera is formed only by a CCD, a sample-and-hold circuit for sampling and holding the output from the CCD, an AGC circuit for adjusting the gain of the output from the sample-and-hold circuit, and an A/D conversion circuit for converting the analog output of the AGC circuit into a digital output.
    Type: Grant
    Filed: September 2, 2004
    Date of Patent: November 14, 2006
    Assignee: Sony Corporation
    Inventors: Tetsujiro Kondo, Hideo Nakaya
  • Patent number: 7113225
    Abstract: A 525i (interlace) signal can be converted into a 1050i signal or a 525p (progressive) signal. A calculating circuit generates pixels of an output picture signal with a linear estimation expression of predictive taps received from a tap selecting circuit and a coefficient received from a coefficient memory. The coefficient memory stores coefficients pre-obtained for individual classes. A class is determined by combining a spatial class corresponding to spatial class taps received from a tap selecting circuit and motion class taps received from a tap selecting circuit. A line sequential converting circuit converts a scanning line structure of an output signal of the calculating circuit 34 and obtains an output picture signal. The output picture signal is designated with a conversion method selection signal. Information corresponding to the selection signal is loaded from an information memory bank to the coefficient memory and registers.
    Type: Grant
    Filed: June 20, 2002
    Date of Patent: September 26, 2006
    Assignee: Sony Corporation
    Inventors: Tetsujiro Kondo, Yasushi Tatehira, Nobuyuki Asakura, Masashi Uchida, Takuo Morimura, Kazutaka Ando, Hideo Nakaya, Tsutomu Watanabe, Satoshi Inoue, Wataru Niitsuma
  • Patent number: 7071930
    Abstract: An active matrix display device includes a pixel array unit having pixels arranged in a matrix pattern, a scanning circuit which sequentially selects pixels in unit of rows, and a signal circuit which receives a video signal containing serial dot data corresponding to each pixel and which writes the dot data into a selected pixel. The signal circuit receives a video signal which includes dot data corresponding to pixels to be rewritten but does not include dot data corresponding to pixels not to be rewritten and which includes skip data defining a skip amount. The signal circuit sequentially processes the dot data and skip data so as to write the corresponding dot data into pixels to be rewritten by skipping pixels not to be rewritten based on the skip data.
    Type: Grant
    Filed: June 25, 2003
    Date of Patent: July 4, 2006
    Assignee: Sony Corporation
    Inventors: Tetsujiro Kondo, Hideo Nakaya, Tsutomu Ichikawa, Takao Inoue
  • Patent number: 7072240
    Abstract: In each of the memory cell arrays in the memory banks, a memory cell row corresponding to each of the word lines extending in a column direction of each of the memory cell arrays store pixel data of each pixel block of first and second rows set in a horizontal way in a search area within a search frame of picture signal. The pixel data of a predetermined pixel block is selectively captured into each of the data buffer through the sense amplifiers and the switches. Selector sequentially extracts pixel data as candidate blocks based on the pixel data of two pixel blocks held in each of the data buffers. The matching circuit matches the pixel data as the extracted candidate blocks against the pixel data as the input reference block using the block-matching process to obtain a motion vector relative to the reference block.
    Type: Grant
    Filed: November 2, 2004
    Date of Patent: July 4, 2006
    Assignee: Sony Corporation
    Inventors: Tetsujiro Kondo, Hiroshi Sato, Hideo Nakaya, Kazutaka Ando
  • Patent number: 7068845
    Abstract: A class synthesizing circuit classifies an aimed-at data item into one of a plurality of classes specified in advance, according to a plurality of data items disposed around the aimed-at data item. A coefficient holding and class-code selection circuit stores conversion information for the aimed-at data item, for each class. An estimation-prediction calculation circuit converts the aimed-at data item to a higher-quality data item according to the conversion information. The class synthesizing circuit classifies the aimed-at data item into a different class according to whether the aimed-at data item is missing.
    Type: Grant
    Filed: February 8, 2001
    Date of Patent: June 27, 2006
    Assignee: Sony Corporation
    Inventors: Tetsujiro Kondo, Hideo Nakaya, Tsutomu Watanabe, Hideki Ohtsuka, Yasuaki Takahashi, Seiji Wada, Takahiro Nagano, Koji Ohta, Hisakazu Shiraki
  • Publication number: 20060126953
    Abstract: JPEG encoded data are entropy-decoded to quantized DCT coefficients which are sent to a prediction tap extraction circuit (41) and to a class tap extraction circuit (42). The prediction tap extraction circuit (41) and the class tap extraction circuit (42) extract what is needed from the quantized DCT coefficients to form prediction taps and class taps. A classification circuit (43) effects classification based on the class taps. A coefficient table storage unit (44) sends tap coefficients corresponding to the classes resulting from the classification to a sum of products circuit (45), which sum of products circuit (45) then effects linear predictive calculations, using the tap coefficients and the class taps, to generate decoded picture data.
    Type: Application
    Filed: February 7, 2006
    Publication date: June 15, 2006
    Inventors: Tetsujiro Kondo, Toshihiko Hamamatsu, Hideo Nakaya, Takeharu Nishikata, Hideki Ohtsuka, Takeshi Kunihiro, Takafumi Morifuji, Masashi Uchida
  • Patent number: 7047325
    Abstract: An integrated processing box performs processing commonly to a plurality of input devices, a plurality of output devices, or a plurality of storage devices. For example, the integrated processing box performs noise reduction processing on data received from an input device or a storage device or data supplied to an output device or the storage device. The integrated processing box also performs processing, for example, temporal/spatial processing or grayscale processing, variably to each type of input device, each type of output device, or each type of storage device. Accordingly, if the input device is, for example, a video camera, the video camera is formed only by a CCD, a sample-and-hold circuit for sampling and holding the output from the CCD, an AGC circuit for adjusting the gain of the output from the sample-and-hold circuit, and an A/D conversion circuit for converting the analog output of the AGC circuit into a digital output.
    Type: Grant
    Filed: May 10, 2001
    Date of Patent: May 16, 2006
    Assignee: Sony Corporation
    Inventors: Tetsujiro Kondo, Hideo Nakaya
  • Publication number: 20060095603
    Abstract: An integrated processing box performs processing commonly to a plurality of input devices, a plurality of output devices, or a plurality of storage devices. For example, the integrated processing box performs noise reduction processing on data received from an input device or a storage device or data supplied to an output device or the storage device. The integrated processing box also performs processing, for example, temporal/spatial processing or grayscale processing, variably to each type of input device, each type of output device, or each type of storage device. Accordingly, if the input device is, for example, a video camera, the video camera is formed only by a CCD, a sample-and-hold circuit for sampling and holding the output from the CCD, an AGC circuit for adjusting the gain of the output from the sample-and-hold circuit, and an A/D conversion circuit for converting the analog output of the AGC circuit into a digital output.
    Type: Application
    Filed: December 15, 2005
    Publication date: May 4, 2006
    Inventors: Tetsujiro Kondo, Hideo Nakaya
  • Patent number: 7035471
    Abstract: JPEG encoded data are entropy-decoded to quantized DCT coefficients which are sent to a prediction tap extraction circuit (41) and to a class tap extraction circuit (42). The prediction tap extraction circuit (41) and the class tap extraction circuit (42) extract what is needed from the quantized DCT coefficients to form prediction taps and class taps. A classification circuit (43) effects classification based on the class taps. A coefficient table storage unit (44) sends tap coefficients corresponding to the classes resulting from the classification to a sum of products circuit (45), which sum of products circuit (45) then effects linear predictive calculations, using the tap coefficients and the class taps, to generate decoded picture data.
    Type: Grant
    Filed: May 9, 2001
    Date of Patent: April 25, 2006
    Assignee: Sony Corporation
    Inventors: Tetsujiro Kondo, Toshihiko Hamamatsu, Hideo Nakaya, Takeharu Nishikata, Hideki Ohtsuka, Takeshi Kunihiro, Takafumi Morifuji, Masashi Uchida
  • Publication number: 20060056516
    Abstract: An image processing apparatus detects a noise area in image data generated by decoding encoded data encoded by a frequency transform method and a lossy compression method. The image processing apparatus includes a motion detection unit for detecting motion in an area having at least one pixel in the image data, a deviation detection unit for detecting the deviation of the image motion in the area having at least one pixel, and a noise detection unit for detecting the noise area in accordance with the deviation of the image motion.
    Type: Application
    Filed: November 2, 2005
    Publication date: March 16, 2006
    Inventors: Toshihiko Hamamatsu, Tetsujiro Kondo, Hideo Nakaya
  • Patent number: 7002587
    Abstract: A semiconductor device and an image data processing apparatus are capable of easily realizing address control, simplifying a circuit for address control, and easily realizing access to image data while reducing the volumes of pieces of image data of different resolutions in different hierarchies. In the image data processing apparatus, a memory cell array stores pieces of composite data, each containing a piece of pixel data and additional information data, for example, a motion vector associated with the pixel data. A designated pixel data and a motion vector associated with the pixel data are read out and a search region is suitably predicted and set up on the basis of the motion vector, and motion estimation is performed in the search region, for example, by a block matching process.
    Type: Grant
    Filed: August 14, 2003
    Date of Patent: February 21, 2006
    Assignee: Sony Corporation
    Inventors: Tetsujiro Kondo, Hideo Nakaya, Kazutaka Ando, Shizuo Chikaoka, Tsutomu Watanabe, Tsutomu Ichikawa, Yasunobu Node, Yoshiaki Nakamura
  • Patent number: 6996184
    Abstract: An image processing apparatus detects a noise area in image data generated by decoding encoded data encoded by a frequency transform method and a lossy compression method. The image processing apparatus includes a motion detection unit for detecting motion in an area having at least one pixel in the image data, a deviation detection unit for detecting the deviation of the image motion in the area having at least one pixel, and a noise detection unit for detecting the noise area in accordance with the deviation of the image motion.
    Type: Grant
    Filed: February 1, 2001
    Date of Patent: February 7, 2006
    Assignee: Sony Corporation
    Inventors: Toshihiko Hamamatsu, Tetsujiro Kondo, Hideo Nakaya