Patents by Inventor Hideo Nakaya

Hideo Nakaya has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 6516088
    Abstract: An NTSC signal is supplied to a first area extracting circuit and a second area extracting circuit. The first area extracting circuit extracts class taps from the NTSC signal. The second area extracting circuit extracts predictive taps from the NTSC signal. The first area extracting circuit extracts pixels in predetermined positions from same phase pixels as a considered pixel. Based on level differences between extracted pixels, a pattern detecting section performs a class categorization. A class code determining section generates class codes based on the result of the class categorization and supplies the generated class codes to a coefficient memory. The coefficient memory outputs pre-stored predictive coefficients based on the class codes to a predictive calculating section.
    Type: Grant
    Filed: October 28, 1999
    Date of Patent: February 4, 2003
    Assignee: Sony Corporation
    Inventors: Tetsujiro Kondo, Takaya Hoshino, Hideo Nakaya, Satoshi Inoue, Shizuo Chikaoka
  • Publication number: 20020186888
    Abstract: JPEG encoded data are entropy-decoded to quantized DCT coefficients which are sent to a prediction tap extraction circuit (41) and to a class tap extraction circuit (42). The prediction tap extraction circuit (41) and the class tap extraction circuit (42) extract what is needed from the quantized DCT coefficients to form prediction taps and class taps. A classification circuit (43) effects classification based on the class taps. A coefficient table storage unit (44) sends tap coefficients corresponding to the classes resulting from the classification to a sum of products circuit (45), which sum of products circuit (45) then effects linear predictive calculations, using the tap coefficients and the class taps, to generate decoded picture data.
    Type: Application
    Filed: June 3, 2002
    Publication date: December 12, 2002
    Inventors: Tetsujiro Kondo, Toshihiko Hamamatsu, Hideo Nakaya, Takeharu Nishikata, Hideki Ohtsuka, Takeshi Kunihiro, Takafumi Morifuji, Masashi Uchida
  • Publication number: 20020181763
    Abstract: A data processing apparatus is capable of executing a plurality of signal processes. The data processing apparatus switches processes of a pre-processing portion, a data processing portion, and a post-processing portion with a control signal supplied from a function controlling portion corresponding to a command supplied from the outside. Thus, the data processing apparatus executes for example processes for increasing the resolution, generating a picture dedicated for a right eye and a picture dedicated for a left eye, generating a luminance signal and color difference signals, changing the aspect ratio, generating pictures having difference resolutions, and converting the frame rate for input data corresponding to a request and outputs picture data generated as the processed result to an external device (for example, a displaying device and a record and reproduction device).
    Type: Application
    Filed: November 28, 2001
    Publication date: December 5, 2002
    Inventors: Tetsujiro Kondo, Hideo Nakaya
  • Publication number: 20020180884
    Abstract: A 525i (interlace) signal can be converted into a 1050i signal or a 525p (progressive) signal. A calculating circuit generates pixels of an output picture signal with a linear estimation expression of predictive taps received from a tap selecting circuit and a coefficient received from a coefficient memory. The coefficient memory stores coefficients pre-obtained for individual classes. A class is determined by combining a spatial class corresponding to spatial class taps received from a tap selecting circuit and motion class taps received from a tap selecting circuit. A line sequential converting circuit converts a scanning line structure of an output signal of the calculating circuit 34 and obtains an output picture signal. The output picture signal is designated with a conversion method selection signal. Information corresponding to the selection signal is loaded from an information memory bank to the coefficient memory and registers.
    Type: Application
    Filed: June 20, 2002
    Publication date: December 5, 2002
    Applicant: SONY CORPORATION
    Inventors: Tetsujiro Kondo, Yasushi Tatehira, Nobuyuki Asakura, Masashi Uchida, Takuo Morimura, Kazutaka Ando, Hideo Nakaya, Tsutomu Watanabe, Satoshi Inoue, Wataru Niitsuma
  • Patent number: 6483546
    Abstract: A picture information converting apparatus for generating an output picture signal with a different scanning line structure from an input picture signal is disclosed, that comprises a first picture data selecting means for selecting adjacent pixels with a predetermined relation of positions to a plurality of considered points with a different relation of positions to scanning lines of the input picture signal, a spatial class detecting means for detecting a pattern of a level distribution from picture data selected by said first picture data selecting means and determining spacial class values that represent spatial classes of the considered points corresponding to the detected pattern, a second picture data selecting means for selecting the considered points and adjacent pixels with the predetermined relation of positions to the considered points from the input picture signal, a calculating process means for performing a calculating process for predicting and generating pixels at positions with a predetermin
    Type: Grant
    Filed: August 20, 1999
    Date of Patent: November 19, 2002
    Assignee: Sony Corporation
    Inventors: Tetsujiro Kondo, Yasushi Tatehira, Nobuyuki Asakura, Masashi Uchida, Takuo Morimura, Kazutaka Ando, Hideo Nakaya, Tsutomu Watanabe, Satoshi Inoue, Wataru Niitsuma
  • Patent number: 6483545
    Abstract: A 525i (interlace) signal can be converted into a 1050i signal or a 525p (progressive) signal. A calculating circuit generates pixels of an output picture signal with a linear estimation expression of predictive taps received from a tap selecting circuit and a coefficient received from a coefficient memory. The coefficient memory stores coefficients pre-obtained for individual classes. A class is determined by combining a spatial class corresponding to spatial class taps received from a tap selecting circuit and motion class taps received from a tap selecting circuit. A line sequential converting circuit converts a scanning line structure of an output signal of the calculating circuit 34 and obtains an output picture signal. The output picture signal is designated with a conversion method selection signal. Information corresponding to the selection signal is loaded from an information memory bank to the coefficient memory and registers.
    Type: Grant
    Filed: July 21, 1999
    Date of Patent: November 19, 2002
    Assignee: Sony Corporation
    Inventors: Tetsujiro Kondo, Yasushi Tatehira, Nobuyuki Asakura, Masashi Uchida, Takuo Morimura, Kazutaka Ando, Hideo Nakaya, Tsutomu Watanabe, Satoshi Inoue, Wataru Niitsuma
  • Publication number: 20020076106
    Abstract: An image processing apparatus includes an object extracting unit, a selecting unit, and an object storing unit. The object extracting unit extracts an object from a target image through a plurality of processing, and outputs the result of extracting the object. The selecting unit selects at least a part of the result of extracting the object which is obtained through the plurality of processing, in accordance with a user's operation. The object storing means stores the result of extracting the object which is selected by the selecting unit.
    Type: Application
    Filed: September 10, 2001
    Publication date: June 20, 2002
    Inventors: Tetsujiro Kondo, Hisakazu Shiraki, Hideo Nakaya, Yuji Okumura
  • Publication number: 20020069211
    Abstract: The present invention permits a re-experience with enhanced realism to be achieved by storing audiovisual signals and bio-signals as experience information. A signal acquirer/encoder collects the audiovisual information and bio-information regarding a user through a plurality of sensors attached to the user, integrates and encodes these signals, and stores the integrated and encoded signals. A storage selects effective information from the integrated signals on the basis of a comprehensive judgment, and stores the effective information. The storage is connected to a rental integrated database that includes a personal database allotted to each user. The user stores enciphered integrated signals in the database allotted to the user. The database is connected to a public database to automatically access associated information. The database and an integrated signal presenter are connected, enabling the user to have a re-experience by means of the integrated signal presenter.
    Type: Application
    Filed: October 4, 2001
    Publication date: June 6, 2002
    Inventors: Tetsujiro Kondo, Hideo Nakaya
  • Patent number: 6356310
    Abstract: A delay register section 31 holds SD pixels of a luminance signal and a classification section 33 decides a class, reads a coefficient corresponding to the decision result from a coefficient RAM section 40, and outputs the coefficient to a product-sum section 38. The product-sum section 38 captures the pixel data for 17 taps from the delay register section 31, converts the pixel data into seven taps, and outputs them to the product-sum section 38. The product-sum section 38 performs the product-sum operation of pixel data and coefficients and outputs the operation result as HD pixels. An interpolation pixel operation section 42 applies a simple interpolation processing different from the case of a luminance signal to the pixel data of a color signal component to generate HD pixels of a color signal. Thus, downsizing and cost reducing can be realized.
    Type: Grant
    Filed: August 3, 2000
    Date of Patent: March 12, 2002
    Assignee: Sony Corporation
    Inventors: Takashi Horishi, Tetsujiro Kondo, Hideo Nakaya
  • Publication number: 20020019892
    Abstract: An integrated processing box performs processing commonly to a plurality of input devices, a plurality of output devices, or a plurality of storage devices. For example, the integrated processing box performs noise reduction processing on data received from an input device or a storage device or data supplied to an output device or the storage device. The integrated processing box also performs processing, for example, temporal/spatial processing or grayscale processing, variably to each type of input device, each type of output device, or each type of storage device. Accordingly, if the input device is, for example, a video camera, the video camera is formed only by a CCD, a sample-and-hold circuit for sampling and holding the output from the CCD, an AGC circuit for adjusting the gain of the output from the sample-and-hold circuit, and an A/D conversion circuit for converting the analog output of the AGC circuit into a digital output.
    Type: Application
    Filed: May 10, 2001
    Publication date: February 14, 2002
    Inventors: Tetsujiro Kondo, Hideo Nakaya
  • Publication number: 20020015528
    Abstract: A class synthesizing circuit classifies an aimed-at data item into one of a plurality of classes specified in advance, according to a plurality of data items disposed around the aimed-at data item. A coefficient holding and class-code selection circuit stores conversion information for the aimed-at data item, for each class. An estimation-prediction calculation circuit converts the aimed-at data item to a higher-quality data item according to the conversion information. The class synthesizing circuit classifies the aimed-at data item into a different class according to whether the aimed-at data item is missing.
    Type: Application
    Filed: February 8, 2001
    Publication date: February 7, 2002
    Inventors: Tetsujiro Kondo, Hideo Nakaya, Tsutomu Watanabe, Hideki Ohtsuka, Yasuaki Takahashi, Seiji Wada, Takahiro Nagano, Koji Ohta, Hisakazu Shiraki
  • Publication number: 20020009097
    Abstract: A signal processing apparatus receives a time divisional multiplexed signal including a plurality of kinds of data. The signal processing apparatus includes a processing unit for processing plural kinds of operations corresponding to the data of the time divisional multiplexed signal, and a changing unit for changing the operation of the processing unit to one of the operations, corresponding to the data at the timing of the transit of the data.
    Type: Application
    Filed: May 25, 2001
    Publication date: January 24, 2002
    Inventors: Tetsujiro Kondo, Hideo Nakaya
  • Publication number: 20010033618
    Abstract: An image processing apparatus detects a noise area in image data generated by decoding encoded data encoded by a frequency transform method and a lossy compression method. The image processing apparatus includes a motion detection unit for detecting motion in an area having at least one pixel in the image data, a deviation detection unit for detecting the deviation of the image motion in the area having at least one pixel, and a noise detection unit for detecting the noise area in accordance with the deviation of the image motion.
    Type: Application
    Filed: February 1, 2001
    Publication date: October 25, 2001
    Inventors: Toshihiko Hamamatsu, Tetsujiro Kondo, Hideo Nakaya
  • Publication number: 20010031069
    Abstract: Picture data of frames [−2] to [+2] of an input picture signal is stored to frame memories fm [−2] to fm [+2]. The picture data of the frame f [0] is supplied to an area extracting circuit. In addition, the picture data of each frame is supplied to a pixel extracting circuit. A horizontal direction DR calculating circuit and a vertical DR calculating circuit calculate a DR in the horizontal direction and a DR in the vertical direction, respectively, and determine the maximum values thereof. A voting range determining circuit and a voting range updating circuit perform a process for finally determining a voting range corresponding to the maximum value of the DR in the horizontal direction and the maximum value of the DR in the vertical direction and a process for designating a new area. A pixel extracting circuit extracts pixels on a straight line defined by straight line parameters.
    Type: Application
    Filed: January 25, 2001
    Publication date: October 18, 2001
    Inventors: Tetsujiro Kondo, Hisakazu Shiraki, Hideo Nakaya, Akira Tange
  • Patent number: 6297855
    Abstract: A simplified Y/C separation circuit in which, a plurality of luminance signals are calculated for the subject pixel based on an NTSC signal of the subject pixel and NTSC signals of pixels that are close to the subject pixel spatially or temporally. Correlations between the plurality of luminance signals are obtained in a difference circuit and a comparison circuit. In a classification circuit, classification is performed, that is, the subject pixel is classified as belonging to a certain class, based on the correlations between the plurality of luminance signals. Prediction coefficients corresponding to the class of the subject pixel are read out from a prediction coefficients memory section. The RGB luminance signals of the subject pixel are then determined by calculating prescribed linear first-order formulae.
    Type: Grant
    Filed: December 22, 1998
    Date of Patent: October 2, 2001
    Assignee: Sony Corporation
    Inventors: Tetsujiro Kondo, Naoki Kobayashi, Hideo Nakaya, Takaya Hoshino, Takeharu Nishikata
  • Patent number: 6285712
    Abstract: An estimation section calculates the motion vector of each pixel and its reliability from two continuous frames, and generates first-order motion distribution images corresponding to the k-th and (k+1)-th frames with any motion vector and reliability being assigned to each pixel. An update section combines the input first-order motion distribution image corresponding to the (k+1)-th frame and the fourth-order motion distribution image corresponding to the (k+1)-th frame generated from the first-order motion distribution image corresponding to the k-th image to generate the second-order motion distribution image corresponding to the (k+1)-th frame. A prediction section generates the third-order motion distribution image corresponding to the (k+2)-th frame according to the input second-order motion distribution image corresponding to the (k+1)-th frame.
    Type: Grant
    Filed: December 28, 1998
    Date of Patent: September 4, 2001
    Assignee: Sony Corporation
    Inventors: Tetsujiro Kondo, Hideo Nakaya, Kenji Tanaka
  • Patent number: 6263105
    Abstract: A block including a subject pixel is formed from an original image. A first class information generation circuit calculates similarity between a decimated block that is obtained by decimating pixels constituting the block and a reduced block obtained by reducing the block (self-similarity of an image). On the other hand, a second class information generation circuit detects a pattern of pixel values of pixels that are arranged in a direction with highest self-similarity in the reduced block (or the decimated block). A final class determination circuit determines a class of the block including the subject pixel based on outputs of both of the first class information generation circuit and the second class information generation circuit. A process corresponding to the thus-determined class is executed.
    Type: Grant
    Filed: April 28, 2000
    Date of Patent: July 17, 2001
    Assignee: Sony Corporation
    Inventors: Hideo Nakaya, Tetsujiro Kondo
  • Patent number: 6233019
    Abstract: The invention concerns a device and a method for converting a first image signal that is comprised of plural pixel data into a second image data that is comprised of plural pixel data. In particular, according to the image converter and the image converting method of the invention, even if the image quality of the inputted image data is poor, it is able to extract the optimal pixel data as the class tap or the predictive tap, and to perform the adequate prediction processing, since clipping of the class tap or the predictive tap is controlled in response to the feature quantity that represents the quantity of fuzz of the inputted image data.
    Type: Grant
    Filed: January 6, 1999
    Date of Patent: May 15, 2001
    Assignee: Sony Corporation
    Inventors: Tetsujiro Kondo, Yasushi Tatehira, Hideo Nakaya, Takaya Hoshino, Masaaki Hattori
  • Patent number: 6201833
    Abstract: A motion determining apparatus for detecting a motion of a partial picture of an input picture signal is disclosed, that comprises a first detecting means for detecting a frame difference of the partial picture, a second detecting means for detecting a spatial activity of the partial picture, a threshold value generating means for generating a first threshold value, a second threshold value, and a third threshold value, a comparing means having at least a first comparing portion for comparing the frame difference detected by said first detecting means with the first threshold value and a second comparing portion for comparing the frame difference detected by said first detecting means with the second threshold value, a third comparing means for comparing the spatial activity detected by said second detecting means with the third threshold value, and a motion class determining means for receiving the compared results of said first comparing portion, said second comparing portion, and said third comparing means
    Type: Grant
    Filed: August 10, 1999
    Date of Patent: March 13, 2001
    Assignee: Sony Corporation
    Inventors: Tetsujiro Kondo, Yasushi Tatehira, Masashi Uchida, Nobuyuki Asakura, Takuo Morimura, Kazutaka Ando, Hideo Nakaya, Tsutomu Watanabe, Satoshi Inoue, Wataru Niitsuma
  • Patent number: 6195463
    Abstract: The present invention relates to a storage device by which image data is hierarchically encoded and stored, and to a technique for reducing the size of the device and increasing processing speed. Size reduction and increased processing speed are realized by hierarchically encoding data stored in memory, by computing higher hierarchical data from lower hierarchy data, and by integrating the memory and the memory accessing circuits all on a single semiconductor chip (e.g., CMOS). The chip includes input writing and output reading, read and write address controllers, memory address decoders, read and write buffers, and a memory cell array.
    Type: Grant
    Filed: July 1, 1998
    Date of Patent: February 27, 2001
    Assignee: Sony Corporation
    Inventors: Tetsujiro Kondo, Hideo Nakaya, Tsutomu Watanabe