Patents by Inventor Hideo Nomura

Hideo Nomura has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240305882
    Abstract: The present technology relates to an imaging device, an imaging method, and a program that enable different imaging elements to align timings at which settings are reflected. The imaging device includes a control unit that controls a second imaging element that captures an image at a lower frame rate than the frame rate of a first imaging element. In a case where a synchronization signal supplied from the first imaging element is received, the control unit determines whether or not the current frame is a frame to be decimated. In a case where the control unit determines that the current frame is not a frame to be decimated, imaging is performed, and in a case where the control unit determines that the current frame is a frame to be decimated, drive for imaging is stopped. The present technology can be applied to an imaging device including a plurality of imaging elements, for example.
    Type: Application
    Filed: February 25, 2022
    Publication date: September 12, 2024
    Inventors: TAKUYA MITSUHASHI, AKIRA HOSOTANI, TETSURO HASHIMOTO, SYUNJI NAGAO, SHINICHI SATO, TAKAHIRO SAKAGUCHI, KAZUHITO KOBAYASHI, HIROKI ABASAKI, HIROAKI ANAI, OSAMU KOBAYAKAWA, HIDEO NOMURA
  • Patent number: 10412329
    Abstract: An imaging apparatus with logarithmic characteristics includes: a photodiode that receives light; a well tap unit that fixes the potential of an N-type region of the photodiode; and a resetting unit that resets the photodiode, a P-type region of the photodiode outputting a voltage signal equivalent to a photocurrent subjected to logarithmic compression. The first potential to be supplied to the well tap unit is made lower than the second potential to be supplied to the resetting unit, so that the capacitance formed with the PN junction of the photodiode is charged when the resetting unit performs a reset operation. The present technology can be applied to unit pixels having logarithmic characteristics.
    Type: Grant
    Filed: November 27, 2015
    Date of Patent: September 10, 2019
    Assignee: Sony Semiconductor Solutions Corporation
    Inventors: Yorito Sakano, Tsutomu Imoto, Hideo Nomura, Yoshiaki Tashiro, Toshiyuki Nishihara, Muriel Cohen, Frederick Brady
  • Publication number: 20170359537
    Abstract: An imaging apparatus with logarithmic characteristics includes: a photodiode that receives light; a well tap unit that fixes the potential of an N-type region of the photodiode; and a resetting unit that resets the photodiode, a P-type region of the photodiode outputting a voltage signal equivalent to a photocurrent subjected to logarithmic compression. The first potential to be supplied to the well tap unit is made lower than the second potential to be supplied to the resetting unit, so that the capacitance formed with the PN junction of the photodiode is charged when the resetting unit performs a reset operation. The present technology can be applied to unit pixels having logarithmic characteristics.
    Type: Application
    Filed: November 27, 2015
    Publication date: December 14, 2017
    Inventors: Yorito SAKANO, Tsutomu IMOTO, Hideo NOMURA, Yoshiaki TASHIRO, Toshiyuki NISHIHARA, Muriel COHEN, Frederick BRADY
  • Patent number: 8687101
    Abstract: A solid-state imaging device includes pixel cells that are formed on a substrate having a first substrate surface side, on which light is irradiated, and a second substrate surface side, on which elements are formed, and separated by an adjacent cell group and an element separation layer for each of the pixel cells or with plural pixel cells as a unit. Each of the pixel cells has a first conductive well formed on the first substrate surface side and a second conductive well formed on the second substrate surface side. The first conductive well receives light from the first substrate surface side and has a photoelectric conversion function and a charge accumulation function for the received light. A transistor that detects accumulated charges in the first conductive well and has a threshold modulation function is formed in the second conductive well.
    Type: Grant
    Filed: January 12, 2012
    Date of Patent: April 1, 2014
    Assignee: Sony Corporation
    Inventors: Isao Hirota, Kouichi Harada, Nobuhiro Karasawa, Yasushi Maruyama, Yoshikazu Nitta, Hiroyuki Terakago, Hajime Takashima, Hideo Nomura
  • Patent number: 8568811
    Abstract: This invention is related to a method of manufacturing a tea drink, which comprises the steps of subjecting tea leaves to extraction to obtain an tea extract and adjusting the pH of the tea extract to the range of 5.0-6.0, mixing nitrogen into the tea extract while applying a negative pressure of 0.01 MPa or more, stabilizing the tea extract in succession to the step of applying a negative pressure by maintaining the tea extract under a pressure of not higher than atmospheric pressure for a period of 30 seconds to 20 minutes, and adjusting the pH of the tea extract to the range of 5.5-6.5 during or subsequent to the step of stabilizing the tea extract.
    Type: Grant
    Filed: March 27, 2009
    Date of Patent: October 29, 2013
    Assignee: Ito En, Ltd.
    Inventors: Masami Sasame, Kenji Shimaoka, Yoko Haraguchi, Izumi Kobayashi, Kazuyoshi Nishimura, Hideo Nomura, Ken-ichi Abe, Tetsuya Onuki
  • Publication number: 20120113292
    Abstract: A solid-state imaging device includes pixel cells that are formed on a substrate having a first substrate surface side, on which light is irradiated, and a second substrate surface side, on which elements are formed, and separated by an adjacent cell group and an element separation layer for each of the pixel cells or with plural pixel cells as a unit. Each of the pixel cells has a first conductive well formed on the first substrate surface side and a second conductive well formed on the second substrate surface side. The first conductive well receives light from the first substrate surface side and has a photoelectric conversion function and a charge accumulation function for the received light. A transistor that detects accumulated charges in the first conductive well and has a threshold modulation function is formed in the second conductive well.
    Type: Application
    Filed: January 12, 2012
    Publication date: May 10, 2012
    Applicant: SONY CORPORATION
    Inventors: Isao Hirota, Kouichi Harada, Nobuhiro Karasawa, Yasushi Maruyama, Yoshikazu Nitta, Hiroyuki Terakago, Hajime Takashima, Hideo Nomura
  • Patent number: 8106983
    Abstract: A solid-state imaging device includes pixel cells that are formed on a substrate having a first substrate surface side, on which light is irradiated, and a second substrate surface side, on which elements are formed, and separated by an adjacent cell group and an element separation layer for each of the pixel cells or with plural pixel cells as a unit. Each of the pixel cells has a first conductive well formed on the first substrate surface side and a second conductive well formed on the second substrate surface side. The first conductive well receives light from the first substrate surface side and has a photoelectric conversion function and a charge accumulation function for the received light. A transistor that detects accumulated charges in the first conductive well and has a threshold modulation function is formed in the second conductive well.
    Type: Grant
    Filed: December 9, 2008
    Date of Patent: January 31, 2012
    Assignee: Sony Corporation
    Inventors: Isao Hirota, Kouichi Harada, Nobuhiro Karasawa, Yasushi Maruyama, Yoshikazu Nitta, Hiroyuki Terakago, Hajime Takashima, Hideo Nomura
  • Patent number: 7907433
    Abstract: A semiconductor device includes a plurality of package terminals included in a package, a plurality of chips provided on the package, each of the chips including a memory cell array and a plurality of data input/output terminals, and a plurality of data line control switch disposed between the plurality of package terminals and the plurality of data input/output terminals. The plurality of data line control switches of each of the chips connects the data input/output terminals of each of the chips to corresponding ones of the plurality of package terminals in a normal mode. The plurality of data line control switches connects different groups of the data input/output terminals in different ones of the chips to respective groups of the package terminals in a test mode. The respective groups of the data input/output terminals belong to the plurality of data input/output terminals. The respective groups of the package terminals are different between different ones of the chips.
    Type: Grant
    Filed: April 24, 2009
    Date of Patent: March 15, 2011
    Assignee: Elpida Memory, Inc.
    Inventors: Hideo Nomura, Tomonori Hayashi, Yuji Sugiyama
  • Publication number: 20090268498
    Abstract: A semiconductor device includes a plurality of package terminals included in a package, a plurality of chips provided on the package, each of the chips including a memory cell array and a plurality of data input/output terminals, and a plurality of data line control switch disposed between the plurality of package terminals and the plurality of data input/output terminals. The plurality of data line control switches of each of the chips connects the data input/output terminals of each of the chips to corresponding ones of the plurality of package terminals in a normal mode. The plurality of data line control switches connects different groups of the data input/output terminals in different ones of the chips to respective groups of the package terminals in a test mode. The respective groups of the data input/output terminals belong to the plurality of data input/output terminals. The respective groups of the package terminals are different between different ones of the chips.
    Type: Application
    Filed: April 24, 2009
    Publication date: October 29, 2009
    Inventors: Hideo Nomura, Tomonori Hayashi, Yuji Sugiyama
  • Publication number: 20090191319
    Abstract: This invention is related to a method of manufacturing a tea drink, which comprises the steps of subjecting tea leaves to extraction to obtain an tea extract and adjusting the pH of the tea extract to the range of 5.0-6.0, mixing nitrogen into the tea extract while applying a negative pressure of 0.01 MPa or more, stabilizing the tea extract in succession to the step of applying a negative pressure by maintaining the tea extract under a pressure of not higher than atmospheric pressure for a period of 30 seconds to 20 minutes, and adjusting the pH of the tea extract to the range of 5.5-6.5 during or subsequent to the step of stabilizing the tea extract.
    Type: Application
    Filed: March 27, 2009
    Publication date: July 30, 2009
    Inventors: Masami Sasame, Kenji Shimaoka, Yoko Haraguchi, Izumi Kobayahsi, Kazuyoshi Nishimura, Hideo Nomura, Ken-ichi Abe, Tetsuya Onuki
  • Publication number: 20090153708
    Abstract: A solid-state imaging device includes pixel cells that are formed on a substrate having a first substrate surface side, on which light is irradiated, and a second substrate surface side, on which elements are formed, and separated by an adjacent cell group and an element separation layer for each of the pixel cells or with plural pixel cells as a unit. Each of the pixel cells has a first conductive well formed on the first substrate surface side and a second conductive well formed on the second substrate surface side. The first conductive well receives light from the first substrate surface side and has a photoelectric conversion function and a charge accumulation function for the received light. A transistor that detects accumulated charges in the first conductive well and has a threshold modulation function is formed in the second conductive well.
    Type: Application
    Filed: December 9, 2008
    Publication date: June 18, 2009
    Applicant: Sony Corporation
    Inventors: Isao Hirota, Kouichi Harada, Nobuhiro Karasawa, Yasushi Maruyama, Yoshikazu Nitta, Hiroyuki Terakago, Hajime Takashima, Hideo Nomura
  • Publication number: 20070143534
    Abstract: A nonvolatile-memory-access control apparatus controls operations for accessing a nonvolatile memory, which include plural cycles by a processing device. The nonvolatile-memory-access control apparatus includes a nonvolatile-memory-access-operation control unit that is capable of setting information on a series of nonvolatile-memory-access operations of the plural cycles, and when a request for access to the nonvolatile memory is received from the processing device, the unit is capable of controlling a series of operations for accessing the nonvolatile memory on the basis of the information set.
    Type: Application
    Filed: December 4, 2006
    Publication date: June 21, 2007
    Applicant: Sony Corporation
    Inventors: Takuya Hashimoto, Kunihiro Miura, Toshinori Nakamura, Hideo Nomura, Kenichi Satori, Kenichi Nakanishi, Naohiro Adachi, Tamaki Konno
  • Patent number: 6328336
    Abstract: A gas generating apparatus for an air bag apparatus mounted in a vehicle or the like for introducing a gas into an air bag to inflate the same for protecting a passenger in the vehicle. The gas generating apparatus for the air bag apparatus according to the present invention ignites and burns a combustible fluid to increase its temperature to increase its pressure for inflating an air bag. The gas generating apparatus for the air bag apparatus includes accommodating device (5) and (9) each for accommodating a combustible fluid (7), a vent opening provided in one of the accommodating device (9), and an occluding member (13) having an igniting portion (14) directed inward of the accommodating device (9). A pressure in the accommodating device is increased by burning the combustible fluid to reliably break the occluding member so that a combustion fluid mixture can effectively and swiftly be supplied to the air bag.
    Type: Grant
    Filed: December 15, 1997
    Date of Patent: December 11, 2001
    Assignees: Matsushita Electric Industrial Co., Ltd., Miyata Industry Co., Ltd.
    Inventors: Hiroyuki Takahashi, Hideo Nomura, Kiyoshi Yamamori, Shigeru Takeyama, Takuhiro Ono, Yoshikazu Kawauchi
  • Patent number: 6194524
    Abstract: A thermoplastic resin composition comprising 100 parts by weight of two or more thermoplastic resins and 0.1 to 100 parts by weight of a polyester having the specific structure, the polyester being added to the thermoplastic resins, wherein a glass transition temperature is not less than 50° C. and/or a deflection temperature under load is not less than 70° C. The present invention provides a high heat-resistant thermoplastic resin composition which is superior in mechanical physical properties and stress crack resistance.
    Type: Grant
    Filed: April 10, 1997
    Date of Patent: February 27, 2001
    Assignee: Sumitomo Chemical Company, Limited
    Inventors: Tohru Nagashima, Hideo Nomura
  • Patent number: 6124390
    Abstract: An aromatic polysulfone resin composition contains 100 parts by weight of an aromatic polysulfone resin and 0.001-50 parts by weight of at least one compound selected from oxides, peroxides, double oxides and carbonates of a metal belonging to the Group IA or IIA in the periodic table of elements and having a water absorption of 2% or less.
    Type: Grant
    Filed: February 12, 1996
    Date of Patent: September 26, 2000
    Assignee: Sumitomo Chemical Company, Limited
    Inventors: Tohru Nagashima, Hideo Nomura
  • Patent number: 6051664
    Abstract: A thermoplastic resin composition includes (a) 1 to 99% by weight of a liquid crystalline polyester and (b) 99 to 1% by weight of a polyester as indispensable components, wherein the polyester is composed of the repeating units represented by the following formulas I, II and III in a specific ratio, ##STR1## wherein, X is --SO.sub.2 --, --CO--, --O--, --S--, --CH.sub.2 --, --CH.sub.2 --CH.sub.2 --, --C(CH.sub.3).sub.2 --, or a single bond; R.sub.1 represents an alkyl group having 1 to 6 carbon atoms, an alkenyl group having 3 to 10 carbon atoms, a phenyl group, or a halogen atom; p is an integer of 0 to 4; m and n are integers of 1 to 4; a plurality of R.sub.1 on the same or different nuclei may be the same or different, and each p may be the same or different.
    Type: Grant
    Filed: June 18, 1997
    Date of Patent: April 18, 2000
    Assignee: Sumitomo Chemical Company, Limited
    Inventors: Tohru Nagashima, Hideo Nomura
  • Patent number: 6013716
    Abstract: Provided is an aromatic polysulfone resin composition comprising 100 parts by weight of an aromatic polysulfone resin compounded with 5 to 240 parts by weight of glass fiber whose surface is treated with an urethane resin. The aromatic polysulfone resin composition is extremely useful as a material for heat-resistant usage including electronic and electric parts because of excellent heat resistance, excellent mechanical properties, high heat stability during mold-procession and low level of gas occluded in the resulting molded article.
    Type: Grant
    Filed: May 15, 1998
    Date of Patent: January 11, 2000
    Assignee: Sumitomo Chemical Company, Limited
    Inventors: Hideo Nomura, Mituo Maeda
  • Patent number: 5976406
    Abstract: A resin composition comprising an inorganic filler in the form of fiber or plate compounded in a liquid crystal polyester resin composition obtained by compounding 10 to 150 parts by weight of a liquid crystal polyester (B) into 100 parts by weight of a liquid crystal polyester (A), wherein the liquid crystal polyester (A) has a flow temperature of from 310 to 400.degree. C., the liquid crystal polyester (B) has a flow temperature of from 270 to 370.degree. C., the difference between the flow temperature of the liquid crystal polyester (A) and the flow temperature of the liquid crystal polyester (B) is from 10 to 60.degree. C., and the content of the inorganic filler is from 15 to 180 parts by weight based on 100 parts by weight of the total amount of the liquid crystal polyester (A) and the liquid crystal polyester (B).The resin composition is excellent in thin-wall flowability and can provide a molded article having excellent heat resistance and low warpage, and can provide a super thin-wall molded article.
    Type: Grant
    Filed: February 3, 1998
    Date of Patent: November 2, 1999
    Assignee: Sumitomo Chemical Company, Limited
    Inventors: Satoshi Nagano, Hideo Nomura
  • Patent number: 5928586
    Abstract: A melt extrusion processing method of a thermoplastic resin, wherein a thermoplastic resin having a flow temperature of 200.degree. C. or higher is subjected to extrusion processing using a melt kneading type extruder in which a vent port is provided at a downstream position by length L from the most upper stream portion of a melt kneading type extruder screw and L/D is from 4 to 18 (wherein D indicates the screw diameter and D and L are in the same scale unit), while continuously sucking from the said vent port at a reduced pressure of lower then 660 mmHg.The invention provides a method which causes little resin degradation in an extruder to give an extruded article containing small amounts of discolored and degraded materials even when the processing is conducted for a relatively long time.
    Type: Grant
    Filed: October 17, 1997
    Date of Patent: July 27, 1999
    Assignee: Sumitomo Chemical Co., Ltd.
    Inventors: Hideo Nomura, Mituo Maeda
  • Patent number: 5910560
    Abstract: A thermoplastic resin composition comprising an aromatic polycarbonate resin and an aromatic polysulfone resin and having the specific melt viscosity ratio between the two resins in the composition. This composition is excellent in heat resistance and gives a molded article of especially high temperature of deflection under load.
    Type: Grant
    Filed: November 26, 1997
    Date of Patent: June 8, 1999
    Assignee: Sumitomo Chemical Company, Ltd.
    Inventors: Tohru Nagashima, Hiroshi Nakamura, Hideo Nomura, Mituo Maeda