Patents by Inventor Hideo Sakamoto

Hideo Sakamoto has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20200156679
    Abstract: According to one embodiment, an information processing apparatus includes processing circuitry. The processing circuitry reads out diagram information indicating a schedule of at least one vehicle tripping along a trip path, wherein the diagram information includes a plurality of events and the events include stop places and departure times from and/or arrival times at the stop places, and calculates a delay probability distribution for a first event of the plurality of events included in the diagram information. The processing circuitry calculates the delay probability distribution for the first event based on: event-to-event delay time information between the first event and a second event preceding the first event; and a required time interval between the first event and the second event.
    Type: Application
    Filed: September 11, 2019
    Publication date: May 21, 2020
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Tomoshi OTSUKI, Hideo SAKAMOTO, Hideyuki AISU, Takufumi YOSHIDA, Hideki KUBO
  • Patent number: 10203162
    Abstract: To provide a geothermal heat exchanger with high thermal efficiency, which can reduce heat loss to a non-geothermal zone when high-temperature liquid heated in the deep underground is transported to the ground. The geothermal heat exchanger of the present invention includes a liquid transport pipe provided with a liquid lowering pipe to which a heat exchange liquid which is pressurized and supplied, a liquid raising pipe which is disposed on the inside or outside side of the liquid lowering pipe and raises the heat exchange liquid which is descended to the geothermal zone, moved from the lower part and composed of the high-temperature liquid generated by which heat from the geothermal zone is supplied, and an outer thermal insulation layer which is provided on a part or the whole of the outside of the liquid transport pipe at least from the ground surface to the geothermal zone.
    Type: Grant
    Filed: August 31, 2015
    Date of Patent: February 12, 2019
    Assignee: JAPAN NEW ENERGY CO., LTD.
    Inventors: Takehiko Yokomine, Hideo Sakamoto
  • Publication number: 20170292792
    Abstract: To provide a geothermal heat exchanger with high thermal efficiency, which can reduce heat loss to a non-geothermal zone when high-temperature liquid heated in the deep underground is transported to the ground. The geothermal heat exchanger of the present invention includes a liquid transport pipe provided with a liquid lowering pipe to which a heat exchange liquid which is pressurized and supplied, a liquid raising pipe which is disposed on the inside or outside side of the liquid lowering pipe and raises the heat exchange liquid which is descended to the geothermal zone, moved from the lower part and composed of the high-temperature liquid generated by which heat from the geothermal zone is supplied, and an outer thermal insulation layer which is provided on a part or the whole of the outside of the liquid transport pipe at least from the ground surface to the geothermal zone.
    Type: Application
    Filed: August 31, 2015
    Publication date: October 12, 2017
    Applicant: JAPAN NEW ENERGY CO., LTD.
    Inventors: Takehiko YOKOMINE, Hideo SAKAMOTO
  • Patent number: 9703906
    Abstract: A circuit simulation device includes a measurement unit, a calculation unit, and a processing unit. The measurement unit measures first spaces between adjacent contacts of a plurality of first contacts provided on a source diffusion layer in a line in a direction along which a gate electrode of a transistor extends and also a space between adjacent contacts of a plurality of second contacts provided on a drain diffusion layer in a line in the direction, based on layout design data, and second spaces between the first contacts and the gate electrode and spaces between the second contacts and the gate electrode. The calculation unit calculates a fringe capacitance between the gate electrode, the source diffusion layer, and the drain diffusion layer of the transistor, based on the first and second spaces. The processing unit executes layout simulation based on the fringe capacitance of the transistor.
    Type: Grant
    Filed: October 26, 2015
    Date of Patent: July 11, 2017
    Assignee: Renesas Electronics Corporation
    Inventor: Hideo Sakamoto
  • Publication number: 20160210386
    Abstract: A circuit simulation device includes a measurement unit, a calculation unit, and a processing unit. The measurement unit measures first spaces between adjacent contacts of a plurality of first contacts provided on a source diffusion layer in a line in a direction along which a gate electrode of a transistor extends and also a space between adjacent contacts of a plurality of second contacts provided on a drain diffusion layer in a line in the direction, based on layout design data, and second spaces between the first contacts and the gate electrode and spaces between the second contacts and the gate electrode. The calculation unit calculates a fringe capacitance between the gate electrode, the source diffusion layer, and the drain diffusion layer of the transistor, based on the first and second spaces. The processing unit executes layout simulation based on the fringe capacitance of the transistor.
    Type: Application
    Filed: October 26, 2015
    Publication date: July 21, 2016
    Inventor: Hideo SAKAMOTO
  • Patent number: 9394128
    Abstract: This invention provides a transfer method of transferring, from a carrier including a placing portion on which a substrate is placed, and a cover that is superposed on the upper surface of the placing portion in close contact, the substrate held between the placing portion and the cover. The transfer method includes a holding step of holding the substrate and the cover on the placing portion by a holding apparatus, and a moving step of moving the holding apparatus to move the substrate and the cover from the placing portion to a transfer destination. In the holding step, the cover is held by the cover holding unit of the holding apparatus, and the substrate is held by the substrate holding unit of the holding apparatus in parallel postures of the cover and substrate.
    Type: Grant
    Filed: December 16, 2014
    Date of Patent: July 19, 2016
    Assignee: HIRATA CORPORATION
    Inventors: Hideo Sakamoto, Shuichi Komuro
  • Publication number: 20160063729
    Abstract: A surgical simulation model generating method which includes a first process in which a computing unit acquires geometrical information of an organ from a medical image stored in a storage unit, including an image of the organ, and generates volume data for the organ; a second process in which, after the first process, the computing unit forms nodal points by meshing the organ represented by the generated volume data; a third process in which the computing unit generates a simulated membrane that covers the organ represented by the volume data meshed in the second process; and a fourth process in which the computing unit generates a simulated organ by drawing an imaginary line so as to extend from each nodal point formed on a surface of the organ represented by the volume data meshed in the second process in a direction that intersects the simulated membrane.
    Type: Application
    Filed: November 3, 2015
    Publication date: March 3, 2016
    Applicant: Mitsubishi Precision Co., Ltd.
    Inventors: Yoshinobu KUBOTA, Kazuhide MAKIYAMA, Takaaki KIKUKAWA, Manabu NAGASAKA, Hideo SAKAMOTO, Masato OGATA
  • Patent number: 9214095
    Abstract: A surgical simulation model generating method includes: a first process in which a computing unit acquires geometrical information of an organ from a medical image stored in a storage unit, including an image of the organ, and generates volume data for the organ; a second process in which, after the first process, the computing unit forms nodal points by meshing the organ represented by the generated volume data; a third process in which the computing unit generates a simulated membrane that covers the organ represented by the volume data meshed in the second process; and a fourth process in which the computing unit generates a simulated organ by drawing an imaginary line so as to extend from each nodal point formed on a surface of the organ represented by the volume data meshed in the second process in a direction that intersects the simulated membrane and thereby forming a membrane nodal point at a point where the imaginary line intersects the simulated membrane generated in the third process, and by arrang
    Type: Grant
    Filed: June 4, 2010
    Date of Patent: December 15, 2015
    Assignee: MITSUBISHI PRECISION CO., LTD.
    Inventors: Yoshinobu Kubota, Kazuhide Makiyama, Takaaki Kikukawa, Manabu Nagasaka, Hideo Sakamoto, Masato Ogata
  • Publication number: 20150197405
    Abstract: This invention provides a transfer method of transferring, from a carrier including a placing portion on which a substrate is placed, and a cover that is superposed on the upper surface of the placing portion in close contact, the substrate held between the placing portion and the cover. The transfer method includes a holding step of holding the substrate and the cover on the placing portion by a holding apparatus, and a moving step of moving the holding apparatus to move the substrate and the cover from the placing portion to a transfer destination. In the holding step, the cover is held by the cover holding unit of the holding apparatus, and the substrate is held by the substrate holding unit of the holding apparatus in parallel postures of the cover and substrate.
    Type: Application
    Filed: December 16, 2014
    Publication date: July 16, 2015
    Applicant: HIRATA CORPORATION
    Inventors: Hideo SAKAMOTO, Shuichi KOMURO
  • Patent number: 8924324
    Abstract: According to one embodiment, a behavior estimation apparatus includes a storage unit, a first calculation unit, a second calculation unit, and an estimation unit. The storage unit stores first data collecting power values consumed by a consumer in a period. The first calculation unit calculates second data representing a frequency of each power value by using the first data. The second calculation unit calculates a first threshold to divide a first power value from a second power value which is larger than and next to the first power value, among power values corresponding to maximal values of frequencies included in the second data. The estimation unit obtains a power value consumed by the consumer in an estimating period, and estimates the consumer's behavior status in the estimating period by using the power value and the first threshold.
    Type: Grant
    Filed: August 30, 2013
    Date of Patent: December 30, 2014
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Shinya Umeno, Yoshiyuki Sakamoto, Hideo Sakamoto, Takashi Koiso, Shuuichiro Imahara, Ryusei Shingaki, Toru Yano, Ryosuke Takeuchi
  • Publication number: 20140142862
    Abstract: According to one embodiment, a behavior estimation apparatus includes a storage unit, a first calculation unit, a second calculation unit, and an estimation unit. The storage unit stores first data collecting power values consumed by a consumer in a period. The first calculation unit calculates second data representing a frequency of each power value by using the first data. The second calculation unit calculates a first threshold to divide a first power value from a second power value which is larger than and next to the first power value, among power values corresponding to maximal values of frequencies included in the second data. The estimation unit obtains a power value consumed by the consumer in an estimating period, and estimates the consumer's behavior status in the estimating period by using the power value and the first threshold.
    Type: Application
    Filed: August 30, 2013
    Publication date: May 22, 2014
    Applicant: Kabushiki Kaisha Toshiba
    Inventors: Shinya UMENO, Yoshiyuki Sakamoto, Hideo Sakamoto, Takashi Koiso, Shuuichiro Imahara, Ryusei Shingaki, Toru Yano, Ryosuke Takeuchi
  • Patent number: 8532359
    Abstract: Medical image data is utilized, physical values are assigned to body parts based on image information, and the target organs are separated from the image data to prepare a 3D biodata model to thereby realize a data model unique to a patient, having an internal structure, and enabling dynamic simulation of a live body. The same target part of a body is captured by CT and MRI to obtain medical images. Sets of pairs of CT images and MRI images are set, a plurality of features showing the same locations are selected and set from the sets of CT images and MRI images, a conversion coefficient between the CT images and MRI images is obtained, and this conversion coefficient is used to rearrange the MRI images by projection transforms and linear interpolation, combine them with the contours of the CT images, and correct their positions in the contours. Further, the images are used to prepare a 3D data model.
    Type: Grant
    Filed: July 10, 2009
    Date of Patent: September 10, 2013
    Assignees: Mitsubishi Precision Co., Ltd., Riken
    Inventors: Kentaro Takanami, Manabu Nagasaka, Hideo Sakamoto, Masato Ogata, Hideo Yokota, Hiroyuki Shimai
  • Patent number: 8498855
    Abstract: A circuit simulation apparatus is provided with a parameter calculating tool and a circuit simulator. The parameter calculating tool is configured to extract gate spacings between gates of a target MOS transistor and adjacent MOS transistors integrated in an integrated circuit from layout data of the integrated circuit, and to calculate a transistor model parameter corresponding to a threshold voltage of the target MOS transistor based on the extracted gate spacings. The circuit simulator is configured to perform circuit simulation of the integrated circuit by using the calculated transistor model parameter.
    Type: Grant
    Filed: September 25, 2009
    Date of Patent: July 30, 2013
    Assignee: Renesas Electronics Corporation
    Inventor: Hideo Sakamoto
  • Patent number: 8484595
    Abstract: An antenna ratio calculation section extracts components from which two or more independent metal wires are coupled to one of diffusion layer regions based on layout data read from a layout data accumulation section, determines, for each of the components, the area of each of the two or more independent metal wires and electrodes coupled to the respective metal wires, determines an antenna ratio between the area of each of the metal wires and the area of the electrode coupled to the metal wire, and determines a moderation value for moderating a design standard associated with plasma charge damage related to one of the metal wires based on the ratio of the total area of all the metal wires coupled to the one of the diffusion layer regions to the area of the one of the metal wires.
    Type: Grant
    Filed: February 22, 2011
    Date of Patent: July 9, 2013
    Assignee: Renesas Electronics Corporation
    Inventor: Hideo Sakamoto
  • Publication number: 20130066791
    Abstract: There is provided a device for determining a rental capacity of a storage battery in which an appliance load predicting unit predicts a demand amount of a household electrical appliance; a power generator predicting unit predicts a power generation amount of a power generator; a constraint condition creating unit creates a constraint condition including first and second constraint expressions, the former matching the predicted demand amount with total electric power supplied to the household electrical appliance and the latter matching the predicted power generation amount with a sum of a power sale amount to the power supplier, a charge amount into the storage battery, and a supply amount to the household electrical appliance; an objective function creating unit creates an objective function based on a sale benefit function, a rental benefit function, a purchase cost function; and an optimization computing unit optimize the objective function to obtains a rental capacity.
    Type: Application
    Filed: July 6, 2012
    Publication date: March 14, 2013
    Applicant: Kabushiki Kaisha Toshiba
    Inventors: Hideo SAKAMOTO, Kazuto KUBOTA, Shuichiro IMAHARA
  • Publication number: 20120081367
    Abstract: A surgical simulation model generating method includes: a first process in which a computing unit acquires geometrical information of an organ from a medical image stored in a storage unit, including an image of the organ, and generates volume data for the organ; a second process in which, after the first process, the computing unit forms nodal points by meshing the organ represented by the generated volume data; a third process in which the computing unit generates a simulated membrane that covers the organ represented by the volume data meshed in the second process; and a fourth process in which the computing unit generates a simulated organ by drawing an imaginary line so as to extend from each nodal point formed on a surface of the organ represented by the volume data meshed in the second process in a direction that intersects the simulated membrane and thereby forming a membrane nodal point at a point where the imaginary line intersects the simulated membrane generated in the third process, and by arrang
    Type: Application
    Filed: June 4, 2010
    Publication date: April 5, 2012
    Applicant: Mitsubishi Precision Co., Ltd.
    Inventors: Yoshinobu Kubota, Kazuhide Makiyama, Takaaki Kikukawa, Manabu Nagasaka, Hideo Sakamoto, Masato Ogata
  • Publication number: 20110204358
    Abstract: An antenna ratio calculation section extracts components from which two or more independent metal wires are coupled to one of diffusion layer regions based on layout data read from a layout data accumulation section, determines, for each of the components, the area of each of the two or more independent metal wires and electrodes coupled to the respective metal wires, determines an antenna ratio between the area of each of the metal wires and the area of the electrode coupled to the metal wire, and determines a moderation value for moderating a design standard associated with plasma charge damage related to one of the metal wires based on the ratio of the total area of all the metal wires coupled to the one of the diffusion layer regions to the area of the one of the metal wires.
    Type: Application
    Filed: February 22, 2011
    Publication date: August 25, 2011
    Inventor: Hideo SAKAMOTO
  • Publication number: 20110150312
    Abstract: Medical image data is utilized, physical values are assigned to body parts based on image information, and the target organs are separated from the image data to prepare a 3D biodata model to thereby realize a data model unique to a patient, having an internal structure, and enabling dynamic simulation of a live body. The same target part of a body is captured by CT and MRI to obtain medical images. Sets of pairs of CT images and MRI images are set, a plurality of features showing the same locations are selected and set from the sets of CT images and MRI images, a conversion coefficient between the CT images and MRI images is obtained, and this conversion coefficient is used to rearrange the MRI images by projection transforms and linear interpolation, combine them with the contours of the CT images, and correct their positions in the contours. Further, the images are used to prepare a 3D data model.
    Type: Application
    Filed: July 10, 2009
    Publication date: June 23, 2011
    Applicants: MITSUBISHI PRECISION CO., LTD., RIKEN
    Inventors: Kentaro Takanami, Manabu Nagasaka, Hideo Sakamoto, Masato Ogata, Hideo Yokoto, Hiroyuki Shimai
  • Publication number: 20100082308
    Abstract: A circuit simulation apparatus is provided with a parameter calculating tool and a circuit simulator. The parameter calculating tool is configured to extract gate spacings between gates of a target MOS transistor and adjacent MOS transistors integrated in an integrated circuit from layout data of the integrated circuit, and to calculate a transistor model parameter corresponding to a threshold voltage of the target MOS transistor based on the extracted gate spacings. The circuit simulator is configured to perform circuit simulation of the integrated circuit by using the calculated transistor model parameter.
    Type: Application
    Filed: September 25, 2009
    Publication date: April 1, 2010
    Inventor: Hideo Sakamoto
  • Patent number: 7626402
    Abstract: Contact holes (openings) (17) are created in the upper electrode (14) and the dielectric film (15) of a polysilicon-insulator-polysilicon (PIP) capacitive element to form a plurality of evaluation patterns wherein the lower electrode (13) and upper layer wiring lines (20) for measurement are electrically connected through contacts (16). At least four evaluation patterns are created by a combination of two or more values of a distance L with different values of a width W. Since it can be assumed that a difference in the resistance value between the respective evaluation patterns is only due to the effect of a change in a rectangular region (W*L) between the contact holes (openings) (17), it is possible to easily calculate the sheet resistance of the high-resistance portion from a change in the resistance value of each of the measurement patterns.
    Type: Grant
    Filed: August 14, 2007
    Date of Patent: December 1, 2009
    Assignee: NEC Electronics Corporation
    Inventor: Hideo Sakamoto