Abstract: To overcome a problem of increase of test time related to BIST in a conventional semiconductor device, a semiconductor device according to one embodiment includes a plurality of memory arrays having different sizes, a test pattern generation circuit that outputs a test pattern for the memory arrays, and a memory interface circuit that is provided for every memory array and converts an access address. The memory interface circuit shifts a test address output from the test pattern generation circuit in accordance with a shift amount set for every memory array, thereby converting the test address to an actual address of a memory array to be tested.

Abstract: An address generation circuit generates a target address to be tested in a memory. A test data generation circuit generates write data for the address and expected value data for read data from the address. A judgment circuit compares matching/non-matching of the read data and the expected value data, for each address, judges that error correction is possible when the number of non-matching bits is within a range of numbers of bits to be error-corrected by an ECC circuit, and judges that error correction is not possible when the number is not within the range.

Abstract: There is to provide a semiconductor device capable of realizing a start time diagnosis on a non-volatile memory without any external device and any non-volatile memory out of a diagnosis target. The non-volatile memory includes an address space formed by addresses continuously read and a reservation address formed by a single or a plurality of addresses, read after the address space. A previously calculated value fixed data is stored in the reservation address. When all the data stored in the address space and the value fixed data are compressed using a predetermined initial value according to a predetermined compression algorithm, the value fixed data is the data for converging the compression value to a predetermined fixed value (for example, 0).

Abstract: To overcome a problem of increase of test time related to BIST in a conventional semiconductor device, a semiconductor device according to one embodiment includes a plurality of memory arrays having different sizes, a test pattern generation circuit that outputs a test pattern for the memory arrays, and a memory interface circuit that is provided for every memory array and converts an access address. The memory interface circuit shifts a test address output from the test pattern generation circuit in accordance with a shift amount set for every memory array, thereby converting the test address to an actual address of a memory array to be tested.

Abstract: An address generation circuit generates a target address to be tested in a memory. A test data generation circuit generates write data for the address and expected value data for read data from the address. A judgment circuit compares matching/non-matching of the read data and the expected value data, for each address, judges that error correction is possible when the number of non-matching bits is within a range of numbers of bits to be error-corrected by an ECC circuit, and judges that error correction is not possible when the number is not within the range.

Abstract: There is to provide a semiconductor device capable of realizing a start time diagnosis on a non-volatile memory without any external device and any non-volatile memory out of a diagnosis target. The non-volatile memory includes an address space formed by addresses continuously read and a reservation address formed by a single or a plurality of addresses, read after the address space. A previously calculated value fixed data is stored in the reservation address. When all the data stored in the address space and the value fixed data are compressed using a predetermined initial value according to a predetermined compression algorithm, the value fixed data is the data for converging the compression value to a predetermined fixed value (for example, 0).

Abstract: A semiconductor integrated circuit which can perform repair of at least one memory circuit in RAM, etc. and can promote improvement in the degree of integration is provided. The encoding circuit 3 receives the failure bit data fail [0]-fail [7], encodes these eight-bit failure bit data fail [7:0], and outputs four-bit (the number of compressed bits) encoded data ef [3:0] sequentially. This encoded data ef [3:0] can indicate various kinds of failure information about RAM1. The capture circuit 4 latches the encoded data ef [3:0] which satisfies a predetermined latch condition, as latch data cf [3:0]. The capture circuit 4 can perform a serial shift operation of the latch data cf [3:0], and can output serially the latch data cf [3:0] as the serial data output So.

Abstract: A semiconductor integrated circuit which can perform repair of at least one memory circuit in RAM, etc. and can promote improvement in the degree of integration is provided. The encoding circuit 3 receives the failure bit data fail [0]-fail [7], encodes these eight-bit failure bit data fail [7:0], and outputs four-bit (the number of compressed bits) encoded data ef [3:0] sequentially. This encoded data ef [3:0] can indicate various kinds of failure information about RAM1. The capture circuit 4 latches the encoded data ef [3:0] which satisfies a predetermined latch condition, as latch data cf [3:0]. The capture circuit 4 can perform a serial shift operation of the latch data cf [3:0], and can output serially the latch data cf [3:0] as the serial data output So.

Abstract: A semiconductor integrated circuit has a scan path that includes, between the output of the first logic section and the input of the functional block, a parallel path and a serial shift path for serially transferring data, and that includes first selectors for connecting the output of the first logic section or the serial shift path to the input of the functional block, and flip-flops for storing the data. The semiconductor integrated circuit further includes second selectors connected into the serial shift path of the scan path, for connecting the output of the functional block or the serial shift path to the input of the second logic section. Test data is provided from the serial shift path of the scan path to the functional block via the second selectors, and data output from the functional block is output via the second selectors after switching the second selectors.

Abstract: A semiconductor integrated circuit has a scan path that includes, between the output of the first logic section and the input of the functional block, a parallel path and a serial shift path for serially transferring data, and that includes first selectors for connecting the output of the first logic section or the serial shift path to the input of the functional block, and flip-flops for storing the data. The semiconductor integrated circuit further includes second selectors connected into the serial shift path of the scan path, for connecting the output of the functional block or the serial shift path to the input of the second logic section. Test data is provided from the serial shift path of the scan path to the functional block via the second selectors, and data output from the functional block is output via the second selectors after switching the second selectors.

Abstract: A semiconductor integrated circuit has a scan path that includes, between the output of the first logic section and the input of the functional block, a parallel path and a serial shift path for serially transferring data, and that includes first selectors for connecting the output of the first logic section or the serial shift path to the input of the functional block, and flip-flops for storing the data. The semiconductor integrated circuit further includes second selectors connected into the serial shift path of the scan path, for connecting the output of the functional block or the serial shift path to the input of the second logic section. Test data is provided from the serial shift path of the scan path to the functional block via the second selectors, and data output from the functional block is output via the second selectors after switching the second selectors.

Abstract: 32 pseudo-random numbers respectively indicated by 5 bits are successively generated in a test address generating unit, a serial output signal denoting one pair of pseudo-random numbers of 10 bits are input to 10 flip-flops serially arranged in an address shift register for each clock cycle, a read address expressed by a string of bits output from the flip-flops of odd-numbered stages is input to a read port of a RAM to perform a read test for one memory cell of the read address, and a write address expressed by a string of bits output from the flip-flops of even-numbered stages is input to a write port of the RAM to perform a write test for one memory cell of the write address. The read test and the write test for 32 memory cells are alternately performed in 64 clock cycles.

Abstract: A semiconductor integrated circuit has a scan path that includes, between the output of the first logic section and the input of the functional block, a parallel path and a serial shift path for serially transferring data, and that includes first selectors for connecting the output of the first logic section or the serial shift path to the input of the functional block, and flip-flops for storing the data. The semiconductor integrated circuit further includes second selectors connected into the serial shift path of the scan path, for connecting the output of the functional block or the serial shift path to the input of the second logic section. Test data is provided from the serial shift path of the scan path to the functional block via the second selectors, and data output from the functional block is output via the second selectors after switching the second selectors.

Abstract: A semiconductor integrated circuit device has a scan path including parallel paths between a first logic section and a functional block, and a serial shift path for serially transferring data from a scan-in terminal to scan-out terminal. The scan path includes first selectors, flip-flops connected to the outputs of the first selectors, and second selectors interposed into the serial shift path, for connecting one of a set of outputs of the functional block and a set of outputs of the serial shift path to the inputs of a second logic section. The test data from the scan-in terminal is shifted into the functional block via the second and first selectors, and test result data the functional block produces are output from the scan-out terminal after switching the second selectors. It can test the functional block in isolation without increasing the scale of the test circuit.

Abstract: 32 pseudo-random numbers respectively indicated by 5 bits are successively generated in a test address generating unit, a serial output signal denoting one pair of pseudo-random numbers of 10 bits are input to 10 flip-flops serially arranged in an address shift register for each clock cycle, a read address expressed by a string of bits output from the flip-flops of odd-numbered stages is input to a read port of a RAM to perform a read test for one memory cell of the read address, and a write address expressed by a string of bits output from the flip-flops of even-numbered stages is input to a write port of the RAM to perform a write test for one memory cell of the write address. The read test and the write test for 32 memory cells are alternately performed in 64 clock cycles.

Abstract: A semiconductor integrated circuit comprises a logic circuit to be tested by a scan test; and a scan path circuit being constituted by serially connecting a plurality of scan register circuits, each of which includes a compound gate circuit having a first logic gate and a second logic gate, a flip-flop circuit connecting an output of the compound gate circuit to a data input terminal, and a gate circuit connecting a first input thereof to a data output terminal of the flip-flop circuit and connecting a second input thereof to a second connection terminal input by a second shift mode signal, and which connects the compound gate circuit, flip-flop circuit, and gate circuit in this turn, wherein a first input of the first logic gate is connected to the logic circuit to be tested, and a second input thereof is connected to a first connection terminal input by a first shift mode signal, while a first input of the logic gate is connected to an output of the first logic gate and a second input thereof is connected t

Abstract: A semiconductor integrated circuit device with fault analysis function performs test operation for a memory circuit (such as a RAM) in which a comparison control circuit (6) generates a comparison control signal CCMP in order to select one or more memory cells in each memory cell group (34, 35, 36 and 37) corresponding to a single bit, a specified row, a specified bit, or a specified pattern, and then outputs the comparison control signal CCMP to scan flip flops (2, 3, 4 and 5) each including a comparator (292). The comparator (292) performs the comparison operation between data and expected values EXP and then outputs a comparison result only when address signals are input and data are red from memory cells, as the object of test, addressed by these address signals.

Abstract: A semiconductor device comprising a memory circuit, a switch for relieving the memory circuit of its failures, and a logic circuit to be tested, facilitates a test of the logic circuit. When a switch control signal (SET) is “1”, for example, a switch (200) selects predetermined 1-bit data (=c) from a plurality of 1-bit data (=b) outputted in parallel form from a RAM (100) and outputs it to a logic circuit (300), where c<b.

Abstract: In a self-repairing operation, a first self-test of a RAM is performed at a first temperature to obtain a first RAM test result, a RAM built-in self-test circuit judges according to the first RAM test result that a faulty portion exists in the RAM, an LSI built-in self-repair circuit judges that the repair of the faulty portion of the RAM is possible, the LSI built-in self-repair circuit controls a redundancy control circuit to avoid the use of the faulty portion of the RAM in a normal operation, the temperature of the RAM is risen by operating the RAM or a logical circuit in a pseudo-self-test to change the first temperature to a second temperature, a second self-test of the RAM is performed at the second temperature to obtain a second RAM test result, and the LSI built-in self-repair circuit confirms that the repair of the faulty portion of the RAM is possible at each of the first and second temperatures by comparing the second RAM test result with the first RAM test result.

Abstract: To provide a semiconductor integrated circuit having a redundancy-relieved data output function which can carry out a pass/fail test of a selecting operation of a redundancy-relieved output selecting circuit for redundancy-relieved output data. Data inputs D of scan flip-flops SFFC <i+3>, SFFC <i+2>, SFFC <i+1> and SFFC <i> are connected to redundancy-relieved output data XDO <i+3>, XDO <i+2>, XDO <i+1> and XDO <i> in place of output data DO <i+3>, DO <i+2>, DO <i+1> and DO <i> of a conventional RAM 211, respectively. An AND gate 21 receives a serial output SO <i+4> at one of inputs and receives a selector test signal PFIN at the other input, and an output thereof is sent to the other input of an AND gate 223.