Abstract: A signal-processing apparatus includes an instruction-parallel processor, a first data-parallel processor, a second data-parallel processor, and a motion detection unit, a de-blocking filtering unit and a variable-length coding/decoding unit which are dedicated hardware. With this structure, during signal processing of an image compression and decompression algorithm needing a large amount of processing, the load is distributed between software and hardware, so that the signal-processing apparatus can realize high processing capability and flexibility.

Abstract: A signal-processing apparatus includes an instruction-parallel processor, a first data-parallel processor, a second data-parallel processor, and a motion detection unit, a de-blocking filtering unit and a variable-length coding/decoding unit which are dedicated hardware. With this structure, during signal processing of an image compression and decompression algorithm needing a large amount of processing, the load is distributed between software and hardware, so that the signal-processing apparatus can realize high processing capability and flexibility.

Abstract: A signal-processing apparatus includes an instruction-parallel processor, a first data-parallel processor, a second data-parallel processor, and a motion detection unit, a de-blocking filtering unit and a variable-length coding/decoding unit which are dedicated hardware. With this structure, during signal processing of an image compression and decompression algorithm needing a large amount of processing, the load is distributed between software and hardware, so that the signal-processing apparatus can realize high processing capability and flexibility.

Abstract: An electret type vibration detection system has a vibration-powered generator that performs vibration-induced power generation by displacing on a basis of external vibration an electret group formed of a plurality of electrets and an electrode group having a plurality of electrode pairs in a relative movement direction to output a vibration-induced voltage between electrodes of the electrode pair, and a transfer function memory section that stores transfer function information that defines a correlation between a vibration velocity of the external vibration and an output power voltage of the vibration-powered generator in a range of a predetermined frequency included in the external vibration, wherein the transfer function information contains a transfer coefficient set according to each of a plurality of frequencies belonging to the predetermined frequency range to place the vibration velocity of the external vibration and the output power voltage of the vibration-powered generator in a predetermined proport

Abstract: A processor executes a plurality of tasks by switching a timeslot and iterating a plurality of timeslots. The processor includes a table in which tasks are defined in correspondence with timeslots. In the table, the number of timeslots to be held in one iteration is defined, for each of the timeslots a total time period during the predetermined number of iterations is designated, and a plurality of tasks are defined in correspondence with at least one of the timeslots. A timeslot is switched every time a predetermined period elapses. One task is selected and executed by referring to the table in correspondence with switching of timeslot.

Abstract: A Very Long Instruction Word (VLIW) processor having an instruction set with a reduced size resulting in a small number of bits being necessary to specify registers. The VLIW processor includes a register file, and first through third operation units, and executes a very long instruction word. Further, the very long instruction word includes a register specifying field which specifies a least one of the registers in the register file and a plurality of instructions. The operand of each instruction includes bits src1, src2, and dst, which indicate whether or not the registers specified by the register specifying field are to be used as the source register and the destination register.

Abstract: A rendering device provides improved rendering responsiveness in multi-window display for rendering scenarios in which display sizes of images vary over time, while also reducing required memory bandwidth. The device comprises: a scenario processor 101 for interpreting a rendering scenario and calculating for each frame period a scale-down ratio for each of a plurality of pictures; a plurality of decoders 107 for decoding encoded data of a plurality of videos; a plurality of first scalers for scaling-down the decoded pictures using the scale-down ratios calculated by the scenario processor 101; a memory 106 for storing the scaled-down pictures; a plurality of second scalers 113 for reading the scaled-down pictures from the memory and re-scaling the scaled-down pictures to match the scale-down ratios calculated by the scenario processor for a current frame period; and, a composing unit 115 for composing the re-scaled pictures.

Abstract: An electret type vibration detection system has a vibration-powered generator that performs vibration-induced power generation by displacing on a basis of external vibration an electret group formed of a plurality of electrets and an electrode group having a plurality of electrode pairs in a relative movement direction to output a vibration-induced voltage between electrodes of the electrode pair, and a transfer function memory section that stores transfer function information that defines a correlation between a vibration velocity of the external vibration and an output power voltage of the vibration-powered generator in a range of a predetermined frequency included in the external vibration, wherein the transfer function information contains a transfer coefficient set according to each of a plurality of frequencies belonging to the predetermined frequency range to place the vibration velocity of the external vibration and the output power voltage of the vibration-powered generator in a predetermined proport

Abstract: A Very Long Instruction Word (VLIW) processor having an instruction set with a reduced size resulting in a small number of bits being necessary to specify registers. The VLIW processor includes a register file, and first through third operation units, and executes a very long instruction word. Further, the very long instruction word includes a register specifying field which specifies a least one of the registers in the register file and a plurality of instructions. The operand of each instruction includes bits src1, src2, and dst, which indicate whether or not the registers specified by the register specifying field are to be used as the source register and the destination register.

Abstract: A processor executes a plurality of tasks by switching a timeslot and iterating a plurality of timeslots. The processor includes a table in which tasks are defined in correspondence with timeslots. In the table, the number of timeslots to be held in one iteration is defined, for each of the timeslots a total time period during the predetermined number of iterations is designated, and a plurality of tasks are defined in correspondence with at least one of the timeslots. A timeslot is switched every time a predetermined period elapses. One task is selected and executed by referring to the table in correspondence with switching of timeslot.

Abstract: A Very Long Instruction Word (VLIW) processor having an instruction set with a reduced size resulting in a small number of bits being necessary to specify registers. The VLIW processor includes a register file, and first through third operation units, and executes a very long instruction word. Further, the very long instruction word includes a register specifying field which specifies a least one of the registers in the register file and a plurality of instructions. The operand of each instruction includes bits src1, src2, and dst, which indicate whether or not the registers specified by the register specifying field are to be used as the source register and the destination register.

Abstract: The present invention provides an information processing apparatus and an integrated circuit which realize parallel execution of different processing systems, and which do not require the provision of a dedicated memory storing instructions for common processing The information processing apparatus comprises: a plurality of processor elements; an instruction memory storing a first program and a second program; and an arbiter interposed between the processor elements and the instruction memory, the arbiter receiving, from each of the processor elements, a request for an instruction, from among instructions included in the first program and the second program, and controlling access to the instruction memory by the processor elements, wherein the arbiter arbitrates requests made by the processor elements when the requests are (i) simultaneous requests for different instructions included in one of the first program and the second program or (ii) simultaneous requests for an instruction included in the first prog

Abstract: A processor for sequentially executing a plurality of programs using a plurality of register value groups stored in a memory that correspond one-to-one with the programs.

Abstract: A rendering device provides improved rendering responsiveness in multi-window display for rendering scenarios in which display sizes of images vary over time, while also reducing required memory bandwidth. The device comprises: a scenario processor 101 for interpreting a rendering scenario and calculating for each frame period a scale-down ratio for each of a plurality of pictures; a plurality of decoders 107 for decoding encoded data of a plurality of videos; a plurality of first scalers for scaling-down the decoded pictures using the scale-down ratios calculated by the scenario processor 101; a memory 106 for storing the scaled-down pictures; a plurality of second scalers 113 for reading the scaled-down pictures from the memory and re-scaling the scaled-down pictures to match the scale-down ratios calculated by the scenario processor for a current frame period; and, a composing unit 115 for composing the re-scaled pictures.

Abstract: The present invention provides an information processing apparatus and an integrated circuit which realize parallel execution of different processing systems, and which do not require the provision of a dedicated memory storing instructions for common processing The information processing apparatus comprises: a plurality of processor elements; an instruction memory storing a first program and a second program; and an arbiter interposed between the processor elements and the instruction memory, the arbiter receiving, from each of the processor elements, a request for an instruction, from among instructions included in the first program and the second program, and controlling access to the instruction memory by the processor elements, wherein the arbiter arbitrates requests made by the processor elements when the requests are (i) simultaneous requests for different instructions included in one of the first program and the second program or (ii) simultaneous requests for an instruction included in the first prog

Abstract: An arithmetic processing apparatus capable of performing an arithmetic operation for generating a condition flag commonly referred to by using a condition flag generated on an arithmetic operation unit basis in as few steps as possible is provided. The arithmetic processing apparatus, which processes multiple data in parallel based on single instruction, includes: processing elements capable of performing a common arithmetic operation based on the evaluation result of the instruction stored in the instruction register; and a condition flag arithmetic operation unit capable of performing one of the logical operation and the comparison operation on the condition flag retained in each processing element, transferring the operation result to each processing element, and updating the condition flag based on the operation result.

Abstract: An information processing apparatus performs switching between an exception handler and normal processing. The information processing apparatus includes a processor; a data processing unit that performs particular processing upon receiving a processing request from the processor; an interrupt controller that issues an interrupt request to the processor; and an exception control unit that controls the interrupt controller, wherein the data processing unit is connected with the exception control unit via a dedicated line. The data processing unit includes a notification unit that notifies, via the dedicated line, the exception control unit of status information indicating current status of the data processing unit, and based on the notified status information and setup information set by the processor, the exception control unit judges whether to cause the interrupt controller to issue an interrupt request to execute an exception handler to the processor.

Abstract: An image encoding device encodes moving pictures, a moving picture count acquisition unit acquires a moving picture count of encoding target moving pictures corresponding to an arbitrary number of input moving pictures, a moving picture acquisition unit acquires one or plural encoding target moving pictures, a processing method designation unit, in accordance with the acquired count, designates processing methods relating to encoding processing that affect a computation amount, and an encoding processing unit performs encoding processing with respect to the acquired one or plural moving pictures, using time division when the plural moving pictures are plural. The encoding unit performs encoding processing using the designated methods.

Abstract: A processor for sequentially executing a plurality of programs using a plurality of register value groups stored in a memory that correspond one-to-one with the programs.

Abstract: A signal processing device includes a first and a second reconfigurable circuit whose logic configuration can be changed. With the reconfigurable circuits sequentially reconfigured, the signal processing device conducts processes regarding signals transmitted to and from a connected external device. At a first temporal point that is after completion of reconfiguration of the first reconfigurable circuit based on the first configuration information and before completion of reconfiguration of the second reconfigurable circuit based on the second reconfigurable circuit, a signal transmission path is formed between an external interface connected to the external device and an internal interface connected to an internal device, with the first reconfigurable circuit inserted into the signal transmission path.