Patents by Inventor Hideshi Nishida
Hideshi Nishida has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20080046704Abstract: A processor according to the present invention includes a decoding unit 20, an operation unit 40 and others. When the decoding unit 20 decodes Instruction vcchk, the operation unit 40 and the like judges whether vector condition flags VC0˜VC3 (110) of a condition flag register (CFR) 32 are all zero or not, and (i) sets condition flags C4 and C5 of the condition flag register (CFR) 32 to 1 and 0, respectively, when all of the vector condition flags VC0˜VC3 are zero, and (ii) sets the condition flags C4 and C5 to 0 and 1, respectively, when not all the vector condition flags are zero. Then, the vector condition flags VC0˜VC3 are stored in the condition flags C0˜C3.Type: ApplicationFiled: August 31, 2007Publication date: February 21, 2008Inventors: Tetsuya Tanaka, Hazuki OKabayashi, Taketo Heishi, Hajime Ogawa, Tsuneyuki Suzuki, Tokuzo Kiyohara, Takeshi Tanaka, Hideshi Nishida, Masaki Maeda
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Publication number: 20080046687Abstract: A processor according to the present invention includes a decoding unit 20, an operation unit 40 and others. When the decoding unit 20 decodes Instruction vcchk, the operation unit 40 and the like judges whether vector condition flags VC0˜VC3 (110) of a condition flag register (CFR) 32 are all zero or not, and (i) sets condition flags C4 and C5 of the condition flag register (CFR) 32 to 1 and 0, respectively, when all of the vector condition flags VC0˜VC3 are zero, and (ii) sets the condition flags C4 and C5 to 0 and 1, respectively, when not all the vector condition flags are zero. Then, the vector condition flags VC0˜VC3 are stored in the condition flags C0˜C3.Type: ApplicationFiled: August 31, 2007Publication date: February 21, 2008Inventors: Tetsuya Tanaka, Hazuki Okabayashi, Taketo Heishi, Hajime Ogawa, Tsuneyuki Suzuki, Tokuzo Kiyohara, Takeshi Tanaka, Hideshi Nishida, Masaki Maeda
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Publication number: 20080046688Abstract: A processor according to the present invention includes a decoding unit 20, an operation unit 40 and others. When the decoding unit 20 decodes Instruction vcchk, the operation unit 40 and the like judges whether vector condition flags VC0˜VC3 (110) of a condition flag register (CFR) 32 are all zero or not, and (i) sets condition flags C4 and C5 of the condition flag register (CFR) 32 to 1 and 0, respectively, when all of the vector condition flags VC0˜VC3 are zero, and (ii) sets the condition flags C4 and C5 to 0 and 1, respectively, when not all the vector condition flags are zero. Then, the vector condition flags VC0˜VC3 are stored in the condition flags C0˜C3.Type: ApplicationFiled: August 31, 2007Publication date: February 21, 2008Inventors: Tetsuya Tanaka, Hazuki Okabayashi, Taketo Heishi, Hajime Ogawa, Tsuneyuki Suzuki, Tokuzo Kiyohara, Takeshi Tanaka, Hideshi Nishida, Masaki Maeda
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Publication number: 20080046690Abstract: A processor according to the present invention includes a decoding unit 20, an operation unit 40 and others. When the decoding unit 20 decodes Instruction vcchk, the operation unit 40 and the like judges whether vector condition flags VC0˜VC3 (110) of a condition flag register (CFR) 32 are all zero or not, and (i) sets condition flags C4 and C5 of the condition flag register (CFR) 32 to 1 and 0, respectively, when all of the vector condition flags VC0˜VC3 are zero, and (ii) sets the condition flags C4 and C5 to 0 and 1, respectively, when not all the vector condition flags are zero. Then, the vector condition flags VC0˜VC3 are stored in the condition flags C0˜C3.Type: ApplicationFiled: August 31, 2007Publication date: February 21, 2008Inventors: Tetsuya Tanaka, Hazuki Okabayashi, Taketo Heishi, Hajime Ogawa, Tsuneyuki Suzuki, Tokuzo Kiyohara, Takeshi Tanaka, Hideshi Nishida, Masaki Maeda
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Patent number: 7315934Abstract: A data processor has sixteen processing elements that each include a register file and an arithmetic logic unit. A network unit connects between the register files of the processing elements and the arithmetic logic units of the processing elements. The network unit has a selector for simultaneously performing a plurality of data transfers which are each made from a register file of one processing element to an operation unit of another processing element. With the provision of this selector that can perform such simultaneous data transfers, the processing efficiency of the processing elements can be maintained even if a change occurs in operand assignments and the like.Type: GrantFiled: February 28, 2003Date of Patent: January 1, 2008Assignee: Matsushita Electric Industrial Co., Ltd.Inventors: Hiroyuki Morishita, Atsushi Ito, Satoshi Takashima, Hideshi Nishida, Kozo Kimura, Tokuzo Kiyohara, Akira Miyoshi, Hiroshi Kadota
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Patent number: 7281117Abstract: A processor according to the present invention includes a decoding unit 20, an operation unit 40 and others. When the decoding unit 20 decodes Instruction vcchk, the operation unit 40 and the like judges whether vector condition flags VC0˜VC3 (110) of a condition flag register (CFR) 32 are all zero or not, and (i) sets condition flags C4 and C5 of the condition flag register (CFR) 32 to 1 and 0, respectively, when all of the vector condition flags VC0˜VC3 are zero, and (ii) sets the condition flags C4 and C5 to 0 and 1, respectively, when not all the vector condition flags are zero. Then, the vector condition flags VC0˜VC3 are stored in the condition flags C0˜C3.Type: GrantFiled: September 24, 2003Date of Patent: October 9, 2007Assignee: Matsushita Electric Industrial Co., Ltd.Inventors: Tetsuya Tanaka, Hazuki Okabayashi, Taketo Heishi, Hajime Ogawa, Tsuneyuki Suzuki, Tokuzo Kiyohara, Takeshi Tanaka, Hideshi Nishida, Masaki Maeda
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Patent number: 7228064Abstract: The present invention provides an image decoding apparatus that realizes speed-up processing of taking out an MR (macroblock remainder) from a fixed length unit that consists of a first DCT block and the MR, without increasing cost. A Setup processor 3 outputs one out of a plurality of fixed length units that constitute an SB (synchronized block). First, calculation is performed for a length from a beginning of the fixed length unit to a EOB (end of block) that is included in the fixed length unit. The calculated length is then used as an offset in taking out the MR. Then an end portion of a second DCT block that is included in the MR is combined with a corresponding beginning portion of the second DCT block, in order to obtain the complete second DCT block. The complete second DCT block is outputted to a variable length code decoder 13.Type: GrantFiled: August 2, 2002Date of Patent: June 5, 2007Assignee: Matsushita Electric Industrial Co., Ltd.Inventors: Yoshiyuki Wada, Makoto Hirai, Tokuzo Kiyohara, Kosuke Yoshioka, Hideshi Nishida, Yukiharu Ieda
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Patent number: 7185176Abstract: A processor according to the present invention includes a decoding unit, an operation unit and others. When the decoding unit decodes an instruction “vxaddh Rc, Ra, Rb”, an arithmetic and logic/comparison operation unit and others (i) adds the higher 16 bits of a register Ra to the lower 16 bits of the register Rb, stores the result in the higher 16 bits of a register Rc, and in parallel with this, (ii) adds the lower 16 bits of the register Ra to the higher 16 bits of the register Rb, and stores the result in the lower 16 bits of the register Rc.Type: GrantFiled: June 2, 2003Date of Patent: February 27, 2007Assignee: Matsushita Electric Industrial Co., Ltd,Inventors: Tetsuya Tanaka, Hazuki Okabayashi, Taketo Heishi, Hajime Ogawa, Yoshihiro Koga, Manabu Kuroda, Masato Suzuki, Tokuzo Kiyohara, Takeshi Tanaka, Hideshi Nishida, Shuji Miyasaka
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Patent number: 7167520Abstract: A transcoder for resizing video data and outputting the resized video data to a reproduction apparatus. The reproduction apparatus reproduces the resized video data by repeating a display period and a non-display period alternately. The transcoder includes: a resizing unit that resizes the video data; and a control unit that causes the resizing unit to resize the video data to first video data having a first resolution so that the reproduction apparatus displays one image during each display period, and causes the resizing unit to resize, during each period between the resizing of the video data to the first video data, the video data to second video data having a second resolution that is lower than the first resolution.Type: GrantFiled: October 15, 2003Date of Patent: January 23, 2007Assignee: Matsushita Electric Industrial Co., Ltd.Inventors: Kosuke Yoshioka, Makoto Hirai, Tetsuji Mochida, Hiroyuki Oka, Hideshi Nishida, Tokuzo Kiyohara
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Patent number: 7020787Abstract: A microprocessor comprises a calculation unit that (i) includes partial calculation units each operable to perform partial data calculation, and (ii) is operable to perform data calculation on N or less bits, where N is a total number of bits on which the partial calculation units are to perform data calculation. The microprocessor, when having the calculation unit perform data calculation according to an instruction fetched from a memory, controls the partial calculation units depending on a bit width mode selected in terms of a number of bits on which data calculation is to be performed, so as to either (i) have all the partial calculation units operate, or (ii) suspend operation of a predetermined number of the partial calculation units, and have the rest of the partial calculation units operate.Type: GrantFiled: December 18, 2002Date of Patent: March 28, 2006Assignee: Matsushita Electric Industrial Co., Ltd.Inventors: Satoshi Takashima, Hideshi Nishida, Kozo Kimura, Tokuzo Kiyohara
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Patent number: 6987811Abstract: The speed of decoding processing for variable-length coded image data is improved.Type: GrantFiled: May 31, 2001Date of Patent: January 17, 2006Assignee: Matsushita Electric Industrial Co., Ltd.Inventors: Takaharu Tanaka, Hideshi Nishida, Kosuke Yoshioka, Tokuzo Kiyohara
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Publication number: 20050238095Abstract: A transcoder for resizing video data and outputting the resized video data to a reproduction apparatus. The reproduction apparatus reproduces the resized video data by repeating a display period and a non-display period alternately. The transcoder includes: a resizing unit that resizes the video data; and a control unit that causes the resizing unit to resize the video data to first video data having a first resolution so that the reproduction apparatus displays one image during each display period, and causes the resizing unit to resize, during each period between the resizing of the video data to the first video data, the video data to second video data having a second resolution that is lower than the first resolution.Type: ApplicationFiled: October 15, 2003Publication date: October 27, 2005Inventors: Kosuke Yoshioka, Makoto Hirai, Tetsuji Mochida, Hiroyuki Oka, Hideshi Nishida, Tokuzo Kiyohara
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Publication number: 20050216699Abstract: A processor having a plurality of processing elements and a decoder operable to decode an instruction. Each of the plurality of processing elements includes: a transfer pattern storage unit operable to store a transfer pattern value that indicates a processing element from which data is transferred; a transfer unit operable to perform a data transfer from the processing element indicated by the transfer pattern value; and an update unit operable to update the transfer pattern value stored in the transfer pattern storage unit, in accordance with a result of decoding a latest instruction by the decoder.Type: ApplicationFiled: February 9, 2005Publication date: September 29, 2005Inventors: Takeshi Tanaka, Hideshi Nishida, Masashi Hoshino, Takeshi Furuta
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Publication number: 20050182916Abstract: A VLIW processor which has an instruction set whose size is reduced so that a small number of bits are necessary to specify registers is provided. The VLIW processor 10 comprises the register file 12, the first-the third operation units 14a-14c and the like, and executes the very long instruction word. And, the very long instruction word includes the register specifying field which specifies a least one of the registers in the register file 12 and a plurality of instructions. The operand of each instruction has the bits, src1 src2 and dst, indicating whether or not the registers specified by the register specifying field are to be used as the source register and the destination register.Type: ApplicationFiled: September 27, 2004Publication date: August 18, 2005Inventors: Takahiro Kageyama, Hideshi Nishida, Takeshi Tanaka, Kouji Nakajima
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Publication number: 20050138326Abstract: A parallel operation apparatus of a SIMD type comprises a processor element group of the SIMD type including a plurality of processor elements, wherein the respective processor elements simultaneously execute an identical operation, a data memory accessible from the respective processor elements in the processor element group, and an address conversion unit for converting an address with respect to the data memory accessed by the processor elements in accordance with a control signal by changing bit positions of the address. The address conversion unit preferably rearranges a first bit, a second bit, and a third bit from a lower order of address data into the second bit, the third bit, and the first bit from the lower order in the change of the bit positions.Type: ApplicationFiled: December 13, 2004Publication date: June 23, 2005Inventors: Kengo Terada, Takeshi Tanaka, Hideshi Nishida
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Patent number: 6901454Abstract: A circuit group control system which receives from a master processor a first command sequence and a second command sequence each of which is composed of a plurality of commands, each command being to be executed by one of a plurality of circuits, and causes any available circuits to execute the commands one by one in order of arrangement in each command sequence. The circuit group control system achieves concurrent execution of a plurality of command sequences by causing a circuit (a second circuit) to execute a command in the second command sequence while another circuit (a first circuit) is executing another command in the first command sequence.Type: GrantFiled: November 7, 2002Date of Patent: May 31, 2005Assignee: Matsushita Electric Industrial Co., Ltd.Inventors: Nobuo Higaki, Tetsuya Tanaka, Kunihiko Hayashi, Hiroshi Kadota, Tokuzo Kiyohara, Kozo Kimura, Hideshi Nishida
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Publication number: 20050088324Abstract: An arithmetic decoding device comprises an adaptive arithmetic decoding unit, a context calculating unit, and a decoding control unit. The adaptive arithmetic decoding unit includes an arithmetic decoding unit, a symbol appearing probability control unit, and a probability state storing unit. When a variable-length encoded code (VLC) is inputted, the context calculating unit generates a context number from a classification and a decoded bit number of a syntax element of the inputted code, and outputs the context number to the adaptive arithmetic decoding unit. The adaptive arithmetic decoding unit renews a symbol appearing probability based on the frequency of appearance of the symbol, thereby arithmetic-decoding the inputted code (VLC), and feeding output data (OD). The decoding control unit controls the whole arithmetic decoding device.Type: ApplicationFiled: October 20, 2004Publication date: April 28, 2005Inventors: Ikuo Fuchigami, Tomonori Kataoka, Hiroaki Toida, Hideshi Nishida
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Publication number: 20050062746Abstract: A signal-processing apparatus comprises an instruction-parallel processor, a first data-parallel processor, a second data-parallel processor, and a motion detection unit, a de-blocking filtering unit and a variable-length coding/decoding unit which are dedicated hardware. With this structure, in signal processing of an image compression and decompression algorithm with a large processing amount, the load is distributed between software and hardware, so that the signal-processing apparatus can realize high processing capability and flexibility.Type: ApplicationFiled: August 17, 2004Publication date: March 24, 2005Inventors: Tomonori Kataoka, Hideshi Nishida, Kouzou Kimura, Nobuo Higaki, Tokuzu Kiyohara
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Publication number: 20050053290Abstract: A decoding apparatus lightens the load incurred by padding processing. When the decoding apparatus outputs decoded data to a frame memory, a padding unit in the decoding apparatus judges whether the decoded data includes boundary pixels, and when boundary pixels are judged to be included, performs padding processing to an extension area using boundary pixel data. As a result, as well as pixels in one decoded macroblock being output, when boundary pixels are included in the output macroblock, the boundary pixels are output to the extension area. This eliminates the need to re-read the boundary pixels from the frame memory.Type: ApplicationFiled: July 21, 2004Publication date: March 10, 2005Inventors: Yoshiyuki Wada, Kosuke Yoshioka, Hideshi Nishida
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Publication number: 20050018914Abstract: The invention provides a circuit used in a padding and other processes necessary for coding of objects, and performs at high speed pixel processing to generate pixel values to be assigned to cells, using pixel values in a reference area, which includes cells with and without a pixel value. A cell address outputting unit (i) obtains cell addresses indicating positions of a predetermined number of cells serially arranged and binary signals expressing whether those cells each have a pixel value, and (ii) selects, for each cell, two of the obtained cell addresses corresponding to a part of binary signals each expressing that a cell has a pixel value, and outputs the selected cell addresses. A reading unit reads pixel values of the cells at the outputted cell addresses. An operating unit calculates the average of the two read pixel values and outputs the average as a pixel value.Type: ApplicationFiled: June 10, 2004Publication date: January 27, 2005Inventors: Hiroyuki Oka, Hideshi Nishida, Kosuke Yoshioka, Tokuzo Kiyohara