Patents by Inventor Hidetaka Shigi
Hidetaka Shigi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20090209053Abstract: To achieve high speed exchange of electrical signals between a connection device and a tester, a support member is provided for supporting the connection device, a plurality of pointed contact terminals are arrayed in an area on the probing side, a multilayer film is provided having a plurality of lead out wires electrically connected to the contact terminals and a ground layer enclosing an insulation layer, and a frame is clamped on the rear side of the multilayer film. A clamping member is provided on the frame to make the multilayer film project out to eliminate slack in the multilayer film. A contact pressure means is provided for making the tips of the contact terminals contact each of the electrodes with predetermined contact pressure from the support member to the clamping member.Type: ApplicationFiled: March 20, 2009Publication date: August 20, 2009Inventors: Susumu KASUKABE, Terutaka Mori, Akihiko Ariga, Hidetaka Shigi, Takayoshi Watanabe, Ryuji Kono
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Patent number: 7541202Abstract: To achieve high speed exchange of electrical signals between a connection device and a tester, a support member is provided for supporting the connection device, a plurality of pointed contact terminals are arrayed in an area on the probing side, a multiplayer film is provided having a plurality of lead out wires electrically connected to the contact terminals and a ground layer enclosing an insulation layer, and a frame is clamped on the rear side of the multiplayer film. A clamping member is provided on the frame to make the multiplayer film project out to eliminate slack in the multiplayer film. A contact pressure means is provided for making the tips of the contact terminals contact each of the electrodes with predetermined contact pressure from the support member to the clamping member.Type: GrantFiled: September 12, 2007Date of Patent: June 2, 2009Assignee: Renesas Technology Corp.Inventors: Susumu Kasukabe, Terutaka Mori, Akihiko Ariga, Hidetaka Shigi, Takayoshi Watanabe, Ryuji Kono
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Patent number: 7390732Abstract: A semiconductor device capable of facilitating high density mounting at low cost without causing any defective conduction at the time of connection to a substrate, a mounting structure thereof and a method of fabrication thereof, characterized in that pyramidal bump electrodes are bonded onto pad electrodes arranged on a semiconductor chip to form the semiconductor device.Type: GrantFiled: July 15, 1998Date of Patent: June 24, 2008Assignee: Hitachi, Ltd.Inventors: Takayoshi Watanabe, Hidetaka Shigi, Susumu Kasukabe, Terutaka Mori
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Publication number: 20080009082Abstract: To achieve high speed exchange of electrical signals between a connection device and a tester, a support member is provided for supporting the connection device, a plurality of pointed contact terminals are arrayed in an area on the probing side, a multiplayer film is provided having a plurality of lead out wires electrically connected to the contact terminals and a ground layer enclosing an insulation layer, and a frame is clamped on the rear side of the multiplayer film. A clamping member is provided on the frame to make the multiplayer film project out to eliminate slack in the multiplayer film. A contact pressure means is provided for making the tips of the contact terminals contact each of the electrodes with predetermined contact pressure from the support member to the clamping member.Type: ApplicationFiled: September 12, 2007Publication date: January 10, 2008Inventors: Susumu Kasukabe, Terutaka Mori, Akihiko Ariga, Hidetaka Shigi, Takayoshi Watanabe, Ryuji Kono
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Patent number: 7285430Abstract: To achieve high speed exchange of electrical signals between a connection device and a tester, a support member is provided for supporting the connection device, a plurality of pointed contact terminals are arrayed in an area on the probing side, a multiplayer film is provided having a plurality of lead out wires electrically connected to the contact terminals and a ground layer enclosing an insulation layer, and a frame is clamped on the rear side of the multiplayer film. A clamping member is provided on the frame to make the multiplayer film project out to eliminate slack in the multiplayer film. A contact pressure means is provided for making the tips of the contact terminals contact each of the electrodes with predetermined contact pressure from the support member to the clamping member.Type: GrantFiled: June 23, 2004Date of Patent: October 23, 2007Assignee: Hitachi, Ltd.Inventors: Susumu Kasukabe, Terutaka Mori, Akihiko Ariga, Hidetaka Shigi, Takayoshi Watanabe, Ryuji Kono
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Patent number: 7198962Abstract: Dispersion of load may be kept within an allowance even when a plurality of probes in a large area are pressed in batch by pressing the probes provided in a membrane to a wafer by applying a pressure load to a plurality of places of a plane of pressure members on the side opposite from the wafer in a probe test step/burn-in test step which is one of semiconductor device manufacturing steps. It is then possible to provide semiconductor devices and a manufacturing method thereof which enhance the reliability and productivity of the semiconductor devices by probing a large number of integrated circuits or a large size integrated circuit in the same time.Type: GrantFiled: April 11, 2003Date of Patent: April 3, 2007Assignee: Hitachi, Ltd.Inventors: Ryuji Kohno, Tetsuo Kumazawa, Makoto Kitano, Akihiko Ariga, Yuji Wada, Naoto Ban, Shuji Shibuya, Yasuhiro Motoyama, Kunio Matsumoto, Susumu Kasukabe, Terutaka Mori, Hidetaka Shigi, Takayoshi Watanabe
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Publication number: 20050069277Abstract: An antenna unit for sending out electromagnetic waves of a millimetric-wave band to outside and receiving the wave reflected from a target, and circuits for signal-processing the reflected wave are equipped as a vehicular millimetric-wave radar device. Antenna patterns are formed on a surface of a multilayer base plate formed of plural stacked layers of dielectric plates and an electroconductive layer interposed between each layer. Circuit wiring patterns and electronic components for signal processing of millimetric waves are disposed on the reverse side. Among all the above-mentioned electronic components, only a millimetric-wave signal oscillator, amplifier, and frequency converter are haused in a hermetically sealed section formed in a localized space on a face of the multilayer base plate. The other electronic components are arranged in a non-hermetically structured condition on a periphery of the hermetically sealed section.Type: ApplicationFiled: November 9, 2001Publication date: March 31, 2005Inventors: Terumi Nakazawa, Kenji Tabuchi, Shuji Eguchi, Tsuyoshi Fujita, Hidetaka Shigi
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Publication number: 20040235207Abstract: To achieve high speed exchange of electrical signals between a connection device and a tester, a support member is provided for supporting the connection device, a plurality of pointed contact terminals are arrayed in an area on the probing side, a multiplayer film is provided having a plurality of lead out wires electrically connected to the contact terminals and a ground layer enclosing an insulation layer, and a frame is clamped on the rear side of the multiplayer film. A clamping member is provided on the frame to make the multiplayer film project out to eliminate slack in the multiplayer film. A contact pressure means is provided for making the tips of the contact terminals contact each of the electrodes with predetermined contact pressure from the support member to the clamping member.Type: ApplicationFiled: June 23, 2004Publication date: November 25, 2004Inventors: Susumu Kasukabe, Terutaka Mori, Akihiko Ariga, Hidetaka Shigi, Takayoshi Watanabe, Ryuji Kono
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Patent number: 6759258Abstract: To achieve high speed exchange of electrical signals between a connection device and a tester, a support member is provided for supporting the connection device, a plurality of pointed contact terminals are arrayed in an area on the probing side, a multiplayer film is provided having a plurality of lead out wires electrically connected to the contact terminals and a ground layer enclosing an insulation layer, and a frame is clamped on the rear side of the multiplayer film. A clamping member is provided on the frame to make the multiplayer film project out to eliminate slack in the multiplayer film. A contact pressure means is provided for making the tips of the contact terminals contact each of the electrodes with predetermined contact pressure from the support member to the clamping member.Type: GrantFiled: October 9, 2001Date of Patent: July 6, 2004Assignee: Renesas Technology Corp.Inventors: Susumu Kasukabe, Terutaka Mori, Akihiko Ariga, Hidetaka Shigi, Takayoshi Watanabe, Ryuji Kono
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Publication number: 20030203521Abstract: Dispersion of load may be kept within an allowance even when a plurality of probes in a large area are pressed in batch by pressing the probes provided in a membrane to a wafer by applying a pressure load to a plurality of places of a plane of pressure members on the side opposite from the wafer in a probe test step/burn-in test step which is one of semiconductor device manufacturing steps. It is then possible to provide semiconductor devices and a manufacturing method thereof which enhance the reliability and productivity of the semiconductor devices by probing a large number of integrated circuits or a large size integrated circuit in the same time.Type: ApplicationFiled: April 11, 2003Publication date: October 30, 2003Inventors: Ryuji Kohno, Tetsuo Kumazawa, Makoto Kitano, Akihiko Ariga, Yuji Wada, Naoto Ban, Shuji Shibuya, Yasuhiro Motoyama, Kunio Matsumoto, Susumu Kasukabe, Terutaka Mori, Hidetaka Shigi, Takayoshi Watanabe
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Patent number: 6566150Abstract: Dispersion of load may be kept within an allowance even when a plurality of probes in a large area are pressed in batch by pressing the probes provided in a membrane to a wafer by applying a pressure load to a plurality of places of a plane of pressure members on the side opposite from the wafer in a probe test step/burn-in test step which is one of semiconductor device manufacturing steps. It is then possible to provide semiconductor devices and a manufacturing method thereof which enhance the reliability and productivity of the semiconductor devices by probing a large number of integrated circuits or a large size integrated circuit in the same time.Type: GrantFiled: June 17, 2002Date of Patent: May 20, 2003Assignee: Hitachi, Ltd.Inventors: Ryuji Kohno, Tetsuo Kumazawa, Makoto Kitano, Akihiko Ariga, Yuji Wada, Naoto Ban, Shuji Shibuya, Yasuhiro Motoyama, Kunio Matsumoto, Susumu Kasukabe, Terutaka Mori, Hidetaka Shigi, Takayoshi Watanabe
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Publication number: 20030019663Abstract: A multi-layer wiring substrate capable of high density packaging, and a method of manufacturing the same, in which a carrier substrate, in which through holes can be easily formed in high density corresponding substantially to a pitch of connecting terminals in a semiconductor chip, and build-up layers are formed on the substrate with the application of a conventional build-up technique. When the build-up technique for repeatedly forming insulating layers and wiring layers on a carrier substrate is used to manufacture a multi-layer wiring substrate, the carrier substrate is formed in the following manner. First, an insulating resin layer is formed in a copper foil, in which a plurality of first windows are regularly provided, to cover the copper foil, and the resin layer fills the interior of the windows.Type: ApplicationFiled: September 23, 2002Publication date: January 30, 2003Inventors: Hidetaka Shigi, Naoya Kitamura, Masashi Nishiki, Tetsuya Yamazaki, Takehiko Hasebe, Masayuki Kyooi, Yukio Maeda
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Patent number: 6506982Abstract: A multi-layer wiring substrate capable of high density packaging, and a method of manufacturing the same, in which a carrier substrate, in which through holes can be easily formed in high density corresponding substantially to a pitch of connecting terminals in a semiconductor chip, and build-up layers are formed on the substrate with the application of a conventional build-up technique. When the build-up technique for repeatedly forming insulating layers and wiring layers on a carrier substrate is used to manufacture a multi-layer wiring substrate, the carrier substrate is formed in the following manner. First, an insulating resin layer is formed in a copper foil, in which a plurality of first windows are regularly provided, to cover the copper foil, and the resin layer fills the interior of the windows.Type: GrantFiled: February 10, 2000Date of Patent: January 14, 2003Assignee: Hitachi, Ltd.Inventors: Hidetaka Shigi, Naoya Kitamura, Masashi Nishiki, Tetsuya Yamazaki, Takehiko Hasebe, Masayuki Kyooi, Yukio Maeda
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Publication number: 20020182796Abstract: Dispersion of load may be kept within an allowance even when a plurality of probes in a large area are pressed in batch by pressing the probes provided in a membrane to a wafer by applying a pressure load to a plurality of places of a plane of pressure members on the side opposite from the wafer in a probe test step/burn-in test step which is one of semiconductor device manufacturing steps. It is then possible to provide semiconductor devices and a manufacturing method thereof which enhance the reliability and productivity of the semiconductor devices by probing a large number of integrated circuits or a large size integrated circuit in the same time.Type: ApplicationFiled: June 17, 2002Publication date: December 5, 2002Inventors: Ryuji Kohno, Tetsuo Kumazawa, Makoto Kitano, Akihiko Ariga, Yuji Wada, Naoto Ban, Shuji Shibuya, Yasuhiro Motoyama, Kunio Matsumoto, Susumu Kasukabe, Terutaka Mori, Hidetaka Shigi, Takayoshi Watanabe
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Patent number: 6455335Abstract: Dispersion of load may be kept within an allowance even when a plurality of probes in a large area are pressed in batch by pressing the probes provided in a membrane to a wafer by applying a pressure load to a plurality of places of a plane of pressure members on the side opposite from the wafer in a probe test step/burn-in test step which is one of semiconductor device manufacturing steps. It is then possible to provide semiconductor devices and a manufacturing method thereof which enhance the reliability and productivity of the semiconductor devices by probing a large number of integrated circuits or a large size integrated circuit in the same time.Type: GrantFiled: August 31, 2000Date of Patent: September 24, 2002Assignee: Hitachi, Ltd.Inventors: Ryuji Kohno, Tetsuo Kumazawa, Makoto Kitano, Akihiko Ariga, Yuji Wada, Naoto Ban, Shuji Shibuya, Yasuhiro Motoyama, Kunio Matsumoto, Susumu Kasukabe, Terutaka Mori, Hidetaka Shigi, Takayoshi Watanabe
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Publication number: 20020129323Abstract: To achieve high speed exchange of electrical signals between a connection device and a tester, a support member is provided for supporting the connection device, a plurality of pointed contact terminals are arrayed in an area on the probing side, a multiplayer film is provided having a plurality of lead out wires electrically connected to the contact terminals and a ground layer enclosing an insulation layer, and a frame is clamped on the rear side of the multiplayer film. A clamping member is provided on the frame to make the multiplayer film project out to eliminate slack in the multiplayer film. A contact pressure means is provided for making the tips of the contact terminals contact each of the electrodes with predetermined contact pressure from the support member to the clamping member.Type: ApplicationFiled: October 9, 2001Publication date: September 12, 2002Inventors: Susumu Kasukabe, Terutaka Mori, Akihiko Ariga, Hidetaka Shigi, Takayoshi Watanabe, Ryuji Kono
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Patent number: 6305230Abstract: A connection device and test system is capable of stable, low load damage-free probing of devices under test, which have many pins with a narrow pitch. Furthermore in order to achieve high speed exchange of electrical signals or so-called high frequency electrical signals, a support member is provided for supporting the connection device, a plurality of pointed contact terminals are arrayed in an area on the probing side, a multilayer film is provided having a plurality of lead out wires electrically connected to the contact terminals and a ground layer enclosing an insulation layer, and a frame is clamped on the rear side of the multilayer film.Type: GrantFiled: November 8, 1999Date of Patent: October 23, 2001Assignee: Hitachi, Ltd.Inventors: Susumu Kasukabe, Terutaka Mori, Akihiko Ariga, Hidetaka Shigi, Takayoshi Watanabe, Ryuji Kono
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Publication number: 20010026444Abstract: In the present invention, a thin film capacitor, having a dielectric layer of a metal oxide having perovskite crystal structure, is formed on a first substrate before the capacitor is transferred onto a second substrate on which an electronic circuit has been formed. Thereafter, patterning of the capacitor and electrical connection are to be carried out.Type: ApplicationFiled: January 22, 2001Publication date: October 4, 2001Inventors: Naoki Matsushima, Eiji Matsuzaki, Hidetaka Shigi, Yasunori Narizuka, Tetsuya Yamazaki, Kazuhiko Horikoshi, Yoichi Abe, Shosaku Ishihara, Kiyoshi Ogata, Toshiyuki Arai
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Patent number: 6197603Abstract: Dispersion of a load may be kept within a predetermined allowance even when a plurality of probes in a large area are pressed in batch by pressing the probes provided in a membrane against a wafer by applying a pressure load to a plurality of places on a plane of the pressure members on the side opposite the wafer in a probe test step, burn-in test step which represent typical semiconductor device manufacturing steps. It is then possible to provide semiconductor devices and a manufacturing method thereof which enhance the reliability and productivity of the semiconductor devices by probing a large number of integrated circuits or a large size integrated circuit at the same time.Type: GrantFiled: September 18, 1998Date of Patent: March 6, 2001Assignee: Hitachi, Ltd.Inventors: Ryuji Kohno, Tetsuo Kumazawa, Makoto Kitano, Akihiko Ariga, Yuji Wada, Naoto Ban, Shuji Shibuya, Yasuhiro Motoyama, Kunio Matsumoto, Susumu Kasukabe, Terutaka Mori, Hidetaka Shigi, Takayoshi Watanabe
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Patent number: 6124553Abstract: A multilayer wiring system for preventing the generation of fixing failure due to an organic residue, eliminating an increase in the number of processes and reducing an area necessary for bonding of the cap and its fabrication method. The multilayer wiring board includes at least one wiring layer made of a conductor, at least one insulating layer made of an organic matter and a board. The wiring layer and the insulating layer are alternately laminated on the board and a cap is provided for covering the insulating layer and the wiring layer. The wiring layer has a wiring pattern for forming a wiring and a frame pattern for surrounding the wiring pattern. This frame pattern includes vent holes. The insulating layer has a shield structure made of an inorganic matter around the outer peripheral portion thereof and/or in the interior thereof. The shield structure is formed of the frame patterns continuously connected to each other and the cap is joined to an uppermost layer of the shield structure.Type: GrantFiled: June 20, 1994Date of Patent: September 26, 2000Assignee: Hitachi, Ltd.Inventors: Yasunori Narizuka, Naoki Matsushima, Hidetaka Shigi, Haruhiko Matsuyama