Abstract: A card controller includes an arithmetic processing device. The controller writes data to a semiconductor memory having a first memory block and a second memory block each including a plurality of nonvolatile memory cells each configured to hold at least 2 bits, data in the first memory block and data in the second memory block being each erased at a time. The arithmetic processing device writes the data to the memory cells in the first memory block using an upper bit and a lower bit of the at least 2 bits and writes the data to the memory cells in the second memory block using only the lower bit of the at least 2 bits.

Abstract: A card controller includes an arithmetic processing device. The controller writes data to a semiconductor memory having a first memory block and a second memory block each including a plurality of nonvolatile memory cells each configured to hold at least 2 bits, data in the first memory block and data in the second memory block being each erased at a time. The arithmetic processing device writes the data to the memory cells in the first memory block using an upper bit and a lower bit of the at least 2 bits and writes the data to the memory cells in the second memory block using only the lower bit of the at least 2 bits.

Abstract: A memory system includes a nonvolatile semiconductor memory and a controller. The memory has a plurality memory blocks each including memory cells capable of holding data. The data in each of the memory blocks is erased simultaneously. The data is written simultaneously in pages in each of the memory blocks. Each of the pages is a set of a plurality of memory cells. The controller transfers write data and a first row address to the memory and issues a change instruction for the transferred first row address and a second row address differing from the first row address. The memory writes the write data into the memory cells corresponding to the first row address when the change instruction has not been issued, and writes the write data into the memory cells corresponding to the second row address when the change instruction has been issued.

Abstract: A memory system includes a nonvolatile semiconductor memory and a controller. The memory has a plurality memory blocks each including memory cells capable of holding data. The data in each of the memory blocks is erased simultaneously. The data is written simultaneously in pages in each of the memory blocks. Each of the pages is a set of a plurality of memory cells. The controller transfers write data and a first row address to the memory and issues a change instruction for the transferred first row address and a second row address differing from the first row address. The memory writes the write data into the memory cells corresponding to the first row address when the change instruction has not been issued, and writes the write data into the memory cells corresponding to the second row address when the change instruction has been issued.

Abstract: A semiconductor memory device includes first memory cell transistors, a memory block, and word lines. Each of the first memory cell transistors has a stacked gate including a charge accumulation layer and a control gate and is capable of holding M bits (M?2i, where i is a natural number and M is a natural number greater than or equal to 3) of data. The memory block includes the first memory cell transistors and is erase unit of the data. The data held in the first memory cell transistors included in the memory block is erased simultaneously. The size of data the memory block is capable of holding is L bits (L=2k, where k is a natural number). The word lines connect in common the control gates of the first memory cell transistors.

Abstract: A memory controller includes logical-physical address conversion table, an access number storing section configured to store the number of accesses to read out data from a memory cell in association with a logical address, a storage state checking section configured to check a storage state of data stored in the memory cell at every predetermined number of accesses, and a refresh processing section configured to perform refresh processing to restore the data stored in the memory cell if the storage state of the data is in a predetermined degraded state.

Abstract: A semiconductor memory device includes first memory cell transistors, a memory block, and word lines. Each of the first memory cell transistors has a stacked gate including a charge accumulation layer and a control gate and is capable of holding M bits (M?2i, where i is a natural number and M is a natural number greater than or equal to 3) of data. The memory block includes the first memory cell transistors and is erase unit of the data. The data held in the first memory cell transistors included in the memory block is erased simultaneously. The size of data the memory block is capable of holding is L bits (L=2k, where k is a natural number). The word lines connect in common the control gates of the first memory cell transistors.

Abstract: A semiconductor device includes a nonvolatile semiconductor memory and a controller. The nonvolatile semiconductor memory includes a first memory block configured to hold at least 2 bits data, and a second memory block configured to hold 1-bit data. The data is programmed into the first and second memory blocks in units of page. Each of the pages in the first memory block is assigned to a corresponding bit of the held data. Time required for write varies depending on the bit. The controller instructs the nonvolatile semiconductor memory to program the write data into the first memory block or the second memory block. The controller instructs the nonvolatile semiconductor memory to program the data on any of the pages in the second memory block if a final page of the write data corresponds to the bit requiring the longest time for the write.

Abstract: A memory system with a semiconductor memory device, in which a physical block of n-bits serves as an erase unit, wherein the address management of the memory device is performed by a logical block with m-bits, “m” being larger than “n” and expressed by a power of two, and wherein a n-bit portion continued from the head address in the logical block is defined as a first management unit corresponding to one physical block of the memory device, and a number of the remaining fraction portions each defined as a second management unit are gathered so as to correspond to one physical block of the memory device.

Abstract: A card controller includes an arithmetic processing device. The controller writes data to a semiconductor memory having a first memory block and a second memory block each including a plurality of nonvolatile memory cells each configured to hold at least 2 bits, data in the first memory block and data in the second memory block being each erased at a time. The arithmetic processing device writes the data to the memory cells in the first memory block using an upper bit and a lower bit of the at least 2 bits and writes the data to the memory cells in the second memory block using only the lower bit of the at least 2 bits.

Abstract: A connection base portion of a stripping solution unit storing a stripping solution is connected to an insertion opening of a channel in an insertion portion of an endoscope. A distal end portion of the insertion portion formed with a distal end opening of the channel is attached, with a sealing film, to an opening in a top cover of a bacteria collection container with a filter inside to be sealed from outside. By suction operation of a syringe at a bottom of the bacteria collection container, the stripping solution is sucked into the insertion opening, flows out from the distal end opening through the channel, and is filtered through the filter. A medium is supplied to the filter for cultivation. A result of the cultivation is observed, and an evaluation result as to cleanliness is obtained from presence or absence of bacteria.

Abstract: A card controller includes an arithmetic processing device. The controller writes data to a semiconductor memory having a first memory block and a second memory block each including a plurality of nonvolatile memory cells each configured to hold at least 2 bits, data in the first memory block and data in the second memory block being each erased at a time. The arithmetic processing device writes the data to the memory cells in the first memory block using an upper bit and a lower bit of the at least 2 bits and writes the data to the memory cells in the second memory block using only the lower bit of the at least 2 bits.

Abstract: A semiconductor memory device includes first memory cell transistors, a memory block, and word lines. Each of the first memory cell transistors has a stacked gate including a charge accumulation layer and a control gate and is capable of holding M bits (M?2i, where i is a natural number and M is a natural number greater than or equal to 3) of data. The memory block includes the first memory cell transistors and is erase unit of the data. The data held in the first memory cell transistors included in the memory block is erased simultaneously. The size of data the memory block is capable of holding is L bits (L=2k, where k is a natural number). The word lines connect in common the control gates of the first memory cell transistors.

Abstract: A memory device includes a nonvolatile memory and a controller. The nonvolatile memory includes a storage area having a plurality of memory blocks each including a plurality of nonvolatile memory cells, and a buffer including a plurality of nonvolatile memory cells and configured to temporarily store data, and in which data is erased for each block. If a size of write data related to one write command is not more than a predetermined size, the controller writes the write data to the buffer.

Abstract: A memory system is configured to receive write data each labeled with a logical address from a host device and includes a nonvolatile semiconductor memory and a controller. The memory stores data in units of a first unit area and erases data in units of a second unit area, each of second unit areas consists of a predetermined number of first unit areas. The controller classifies the logical address of the write data into one of management units in accordance with the logical address, manages correspondence information that shows a correspondence between logical addresses of stored data and second unit areas that store corresponding write data for each of the management units, and assigns to the write data one of the second unit areas that have at least as large address space as an address space of logical addresses belonging to two or more of the management units.

Abstract: A memory system includes a nonvolatile semiconductor memory and a controller. The memory has a plurality memory blocks each including memory cells capable of holding data. The data in each of the memory blocks is erased simultaneously. The data is written simultaneously in pages in each of the memory blocks. Each of the pages is a set of a plurality of memory cells. The controller transfers write data and a first row address to the memory and issues a change instruction for the transferred first row address and a second row address differing from the first row address. The memory writes the write data into the memory cells corresponding to the first row address when the change instruction has not been issued, and writes the write data into the memory cells corresponding to the second row address when the change instruction has been issued.

Abstract: A card controller includes an arithmetic processing device. The controller writes data to a semiconductor memory having a first memory block and a second memory block each including a plurality of nonvolatile memory cells each configured to hold at least 2 bits, data in the first memory block and data in the second memory block being each erased at a time. The arithmetic processing device writes the data to the memory cells in the first memory block using an upper bit and a lower bit of the at least 2 bits and writes the data to the memory cells in the second memory block using only the lower bit of the at least 2 bits.