Patents by Inventor Hideto Hashiguchi
Hideto Hashiguchi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11955500Abstract: There is provided a solid-state imaging device including: a first substrate including a first semiconductor substrate and a first wiring layer, the first semiconductor substrate having a pixel unit with pixels; a second substrate including a second semiconductor substrate and a second wiring layer, the second semiconductor substrate having a circuit with a predetermined function; and a third substrate including a third semiconductor substrate and a third wiring layer, the third semiconductor substrate having a circuit with a predetermined function, the first, second, and third substrates being stacked in this order, the first substrate and the second substrate being bonded together with the first wiring layer and the second wiring layer opposed to each other, a first coupling structure on bonding surfaces of the first substrate and the second substrate, and including an electrode junction structure with electrodes formed on the respective bonding surfaces in direct contact with each other.Type: GrantFiled: February 3, 2022Date of Patent: April 9, 2024Assignee: Sony Semiconductor Solutions CorporationInventors: Reijiroh Shohji, Masaki Haneda, Hiroshi Horikoshi, Minoru Ishida, Takatoshi Kameshima, Ikue Mitsuhashi, Hideto Hashiguchi, Tadashi Iijima
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Patent number: 11948961Abstract: A solid-state imaging device including a first substrate on which a pixel unit is formed, and a first semiconductor substrate and a first multi-layered wiring layer are stacked, a second substrate on which a circuit having a predetermined function is formed, and a second semiconductor substrate and a second multi-layered wiring layer are stacked, and a third substrate on which a circuit having a predetermined function is formed, and a third semiconductor substrate and a third multi-layered wiring layer are stacked. The first substrate, the second substrate, and the third substrate are stacked in this order. A first coupling structure for electrically coupling a circuit of the first substrate and the circuit of the second substrate to each other does not include a coupling structure formed from the first substrate as a base over bonding surfaces of the first substrate and the second substrate.Type: GrantFiled: July 20, 2022Date of Patent: April 2, 2024Assignee: SONY SEMICONDUCTOR SOLUTIONS CORPORATIONInventors: Hideto Hashiguchi, Reijiroh Shohji, Hiroshi Horikoshi, Ikue Mitsuhashi, Tadashi Iijima, Takatoshi Kameshima, Minoru Ishida, Masaki Haneda
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Patent number: 11804507Abstract: A solid-state imaging device including a first substrate having a pixel unit formed thereon and including a first semiconductor substrate and a first multi-layered wiring layer stacked, a second substrate having a circuit formed thereon and including a second semiconductor substrate and a second multi-layered wiring layer, the circuit having a predetermined function, and a third substrate having a circuit formed thereon and including a third semiconductor substrate and a third multi-layered wiring layer. The first substrate and the second substrate are bonded together such that that the first multi-layered wiring layer and the second semiconductor substrate are opposed to each other. The solid-state imaging device includes a first coupling structure and a second coupling structure. The first coupling structure electrically couples a circuit of the first substrate and the circuit of the second substrate.Type: GrantFiled: November 23, 2021Date of Patent: October 31, 2023Assignee: SONY SEMICONDUCTOR SOLUTIONS CORPORATIONInventors: Ikue Mitsuhashi, Reijiroh Shohji, Minoru Ishida, Tadashi Iijima, Takatoshi Kameshima, Hideto Hashiguchi, Hiroshi Horikoshi, Masaki Haneda
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Publication number: 20230275020Abstract: Provided is a wiring structure having superior operation reliability. This wiring structure includes a plurality of wiring lines each extending in a first direction and disposed side by side in a second direction orthogonal to the first direction; and a first insulating film that covers the plurality of wiring lines and has a gap present in a gap region sandwiched between the plurality of wiring lines adjacent to each other in the second direction. Herein, the gap has a cross-sectional shape defined by an outline including only one curved line, or a cross-sectional shape defined by an outline that includes one or more curved lines and one or more straight lines coupled at two or more coupling sections and has an intersecting angle of 90° or more between the curved lines, between the straight lines, or between the curved line and the straight line at the coupling section.Type: ApplicationFiled: July 9, 2021Publication date: August 31, 2023Applicant: SONY SEMICONDUCTOR SOLUTIONS CORPORATIONInventors: Hideto HASHIGUCHI, Ikue MITSUHASHI
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Patent number: 11594567Abstract: A solid-state imaging device includes first through third substrates. The first substrate includes a first semiconductor substrate and a first multi-layered wiring layer stacked thereon. The second substrate includes a second semiconductor substrate and a second multi-layered wiring layer stacked thereon. The third substrate includes a third semiconductor substrate and a third multi-layered wiring layer stacked thereon. A coupling structure for electrically coupling at least two of the first through third substrates includes a via. The via exposes a predetermined wiring line in the second multi-layered wiring layer while exposing a portion of a predetermined wiring line in the first multi-layered wiring layer from a back surface side of the first substrate, or exposes a predetermined wiring line in the third multi-layered wiring layer while exposing a portion of the predetermined wiring line in the first multi-layered wiring layer or the second multi-layered wiring layer from the back surface.Type: GrantFiled: March 23, 2018Date of Patent: February 28, 2023Assignee: SONY GROUP CORPORATIONInventors: Tadashi Iijima, Takatoshi Kameshima, Ikue Mitsuhashi, Hiroshi Horikoshi, Hideto Hashiguchi, Reijiroh Shohji, Minoru Ishida, Masaki Haneda
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Publication number: 20230020137Abstract: A solid-state imaging device including: a first substrate having a pixel unit, and a first semiconductor substrate and a first wiring layer; a second substrate with a circuit, and a second semiconductor substrate and a second wiring layer; and a third substrate with a circuit, and a third semiconductor substrate and a third wiring layer. The first and second substrates are bonded together such that the first wiring layer and the second semiconductor substrate are opposed to each other. The device includes a first coupling structure for electrically coupling a circuit of the first substrate and the circuit of the second substrate. The first coupling structure includes a via in which electrically-conductive materials are embedded in a first through hole that exposes a wiring line in the first wiring layer and in a second through hole that exposes a wiring line in the second wiring layer or a film-formed structure.Type: ApplicationFiled: September 27, 2022Publication date: January 19, 2023Applicant: SONY SEMICONDUCTOR SOLUTIONS CORPORATIONInventors: Hideto HASHIGUCHI, Reijiroh SHOHJI, Hiroshi HORIKOSHI, Ikue MITSUHASHI, Tadashi IIJIMA, Takatoshi KAMESHIMA, Minoru ISHIDA, Masaki HANEDA
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Publication number: 20220359603Abstract: A solid-state imaging device is provided that comprises a first substrate that includes a first multi-layered wiring layer stacked on a first semiconductor substrate, a second substrate that includes a second multi-layered wiring layer and an insulating layer stacked on a second semiconductor substrate, and a third substrate that includes a third multi-layered wiring layer stacked on a third semiconductor substrate. A first coupling structure electrically couples the first and second substrates to each other. A second coupling structure exists on bonding surfaces of the second and third substrates, and includes an electrode junction structure in which electrodes formed on respective bonding surfaces are in direct contact with each other. A first via penetrates the second semiconductor substrate and electrically couples a first electrode to a wiring in the second multi-layered wiring layer. A second via electrically couples the second electrode to another wiring in the third multi-layered wiring layer.Type: ApplicationFiled: July 25, 2022Publication date: November 10, 2022Inventors: TAKATOSHI KAMESHIMA, HIDETO HASHIGUCHI, IKUE MITSUHASHI, HIROSHI HORIKOSHI, REIJIROH SHOHJI, MINORU ISHIDA, TADASHI IIJIMA, MASAKI HANEDA
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Publication number: 20220359605Abstract: To provide a solid-state imaging device and an electronic apparatus with further improved performance. A solid-state imaging device including: a first substrate on which a pixel unit is formed, and a first semiconductor substrate and a first multi-layered wiring layer are stacked; a second substrate on which a circuit having a predetermined function is formed, and a second semiconductor substrate and a second multi-layered wiring layer are stacked; and a third substrate on which a circuit having a predetermined function is formed, and a third semiconductor substrate and a third multi-layered wiring layer are stacked. The first substrate, the second substrate, and the third substrate are stacked in this order. The pixel unit has pixels arranged thereon. The first substrate and the second substrate are bonded together in a manner that the first multi-layered wiring layer and the second semiconductor substrate are opposed to each other.Type: ApplicationFiled: July 20, 2022Publication date: November 10, 2022Inventors: HIDETO HASHIGUCHI, REIJIROH SHOHJI, HIROSHI HORIKOSHI, IKUE MITSUHASHI, TADASHI IIJIMA, TAKATOSHI KAMESHIMA, MINORU ISHIDA, MASAKI HANEDA
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Patent number: 11476294Abstract: A solid-state imaging device including: a first substrate having a pixel unit, and a first semiconductor substrate and a first wiring layer; a second substrate with a circuit, and a second semiconductor substrate and a second wiring layer; and a third substrate with a circuit, and a third semiconductor substrate and a third wiring layer. The first and second substrates are bonded together such that the first wiring layer and the second semiconductor substrate are opposed to each other. The device includes a first coupling structure for electrically coupling a circuit of the first substrate and the circuit of the second substrate. The first coupling structure includes a via in which electrically-conductive materials are embedded in a first through hole that exposes a wiring line in the first wiring layer and in a second through hole that exposes a wiring line in the second wiring layer or a film-formed structure.Type: GrantFiled: March 29, 2021Date of Patent: October 18, 2022Assignee: SONY SEMICONDUCTOR SOLUTIONS CORPORATIONInventors: Hideto Hashiguchi, Reijiroh Shohji, Hiroshi Horikoshi, Ikue Mitsuhashi, Tadashi Iijima, Takatoshi Kameshima, Minoru Ishida, Masaki Haneda
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Patent number: 11411037Abstract: [Object] To provide a solid-state imaging device and an electronic apparatus with further improved performance. [Solution] A solid-state imaging device including: a first substrate on which a pixel unit is formed, and a first semiconductor substrate and a first multi-layered wiring layer are stacked; a second substrate on which a circuit having a predetermined function is formed, and a second semiconductor substrate and a second multi-layered wiring layer are stacked; and a third substrate on which a circuit having a predetermined function is formed, and a third semiconductor substrate and a third multi-layered wiring layer are stacked. The first substrate, the second substrate, and the third substrate are stacked in this order. The pixel unit has pixels arranged thereon. The first substrate and the second substrate are bonded together in a manner that the first multi-layered wiring layer and the second semiconductor substrate are opposed to each other.Type: GrantFiled: March 23, 2018Date of Patent: August 9, 2022Assignee: SONY SEMICONDUCTOR SOLUTIONS CORPORATIONInventors: Hideto Hashiguchi, Reijiroh Shohji, Hiroshi Horikoshi, Ikue Mitsuhashi, Tadashi Iijima, Takatoshi Kameshima, Minoru Ishida, Masaki Haneda
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Patent number: 11411036Abstract: A solid-state imaging device includes a first substrate including a first semiconductor substrate and a first multi-layered wiring layer stacked on the first semiconductor substrate, a second substrate including a second semiconductor substrate and a second multi-layered wiring layer stacked on the second semiconductor substrate, a third substrate including a third semiconductor substrate and a third multi-layered wiring layer stacked on the third semiconductor substrate, and a first coupling structure for electrically coupling the first substrate and the second substrate. The first substrate, the second substrate, and the third substrate are stacked in this order. The first substrate and the second substrate are bonded together such that the first multi-layered wiring layer and the second multi-layered wiring layer are opposed to each other. The first substrate excludes a coupling structure formed from the first substrate as a base over bonding surfaces of the first substrate and the second substrate.Type: GrantFiled: March 23, 2018Date of Patent: August 9, 2022Assignee: SONY SEMICONDUCTOR SOLUTIONS CORPORATIONInventors: Takatoshi Kameshima, Hideto Hashiguchi, Ikue Mitsuhashi, Hiroshi Horikoshi, Reijiroh Shohji, Minoru Ishida, Tadashi Iijima, Masaki Haneda
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Publication number: 20220216246Abstract: To provide a solid-state imaging device that makes it possible to further improve reliability of junction. A solid-state imaging device is provided that includes a first substrate including at least a first electrode, a first modification layer, a first low-permittivity layer formed on the first modification layer, and a first joint surface where the first electrode and the first modification layer are exposed; and a second substrate including at least a second electrode, a second modification layer, a second low-permittivity layer formed on the second modification layer, and a second joint surface where the second electrode and the second modification layer are exposed. The first modification layer has higher hydrophilicity than the first low-permittivity layer. The second modification layer has higher hydrophilicity than the second low-permittivity layer.Type: ApplicationFiled: April 6, 2020Publication date: July 7, 2022Inventor: HIDETO HASHIGUCHI
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Publication number: 20220157877Abstract: There is provided a solid-state imaging device including: a first substrate including a first semiconductor substrate and a first wiring layer, the first semiconductor substrate having a pixel unit with pixels; a second substrate including a second semiconductor substrate and a second wiring layer, the second semiconductor substrate having a circuit with a predetermined function; and a third substrate including a third semiconductor substrate and a third wiring layer, the third semiconductor substrate having a circuit with a predetermined function, the first, second, and third substrates being stacked in this order, the first substrate and the second substrate being bonded together with the first wiring layer and the second wiring layer opposed to each other, a first coupling structure on bonding surfaces of the first substrate and the second substrate, and including an electrode junction structure with electrodes formed on the respective bonding surfaces in direct contact with each other.Type: ApplicationFiled: February 3, 2022Publication date: May 19, 2022Applicant: SONY SEMICONDUCTOR SOLUTIONS CORPORATIONInventors: Reijiroh SHOHJI, Masaki HANEDA, Hiroshi HORIKOSHI, Minoru ISHIDA, Takatoshi KAMESHIMA, Ikue MITSUHASHI, Hideto HASHIGUCHI, Tadashi IIJIMA
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Patent number: 11289526Abstract: There is provided a solid-state imaging device including: a first substrate including a first semiconductor substrate and a first wiring layer, the first semiconductor substrate having a pixel unit with pixels; a second substrate including a second semiconductor substrate and a second wiring layer, the second semiconductor substrate having a circuit with a predetermined function; and a third substrate including a third semiconductor substrate and a third wiring layer, the third semiconductor substrate having a circuit with a predetermined function, the first, second, and third substrates being stacked in this order, the first substrate and the second substrate being bonded together with the first wiring layer and the second wiring layer opposed to each other, a first coupling structure on bonding surfaces of the first substrate and the second substrate, and including an electrode junction structure with electrodes formed on the respective bonding surfaces in direct contact with each other.Type: GrantFiled: March 23, 2018Date of Patent: March 29, 2022Assignee: Sony Semiconductor Solutions CorporationInventors: Reijiroh Shohji, Masaki Haneda, Hiroshi Horikoshi, Minoru Ishida, Takatoshi Kameshima, Ikue Mitsuhashi, Hideto Hashiguchi, Tadashi Iijima
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Publication number: 20220085093Abstract: To provide a solid-state imaging device and an electronic apparatus with further improved performance.Type: ApplicationFiled: November 23, 2021Publication date: March 17, 2022Inventors: IKUE MITSUHASHI, REIJIROH SHOHJI, MINORU ISHIDA, TADASHI IIJIMA, TAKATOSHI KAMESHIMA, HIDETO HASHIGUCHI, HIROSHI HORIKOSHI, MASAKI HANEDA
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Publication number: 20220005860Abstract: A semiconductor apparatus and electronic equipment are provided that allow improvement of bondability between a first electrode section and a second electrode section. A semiconductor apparatus includes a first interconnect section, a first interlayer insulating film covering one surface side of the first interconnect section, a first electrode section in a first through-hole in the first interlayer insulating film and electrically connected to the first interconnect section, a second interconnect section, a second interlayer insulating film covering a surface side of the second interconnect section facing the first interconnect section, and a second electrode section in a second through-hole in the second interlayer insulating film and electrically connected to the second interconnect section. The first electrode section and the second electrode section are directly bonded to each other. The first electrode section has a larger coefficient of thermal expansion than that of the first interconnect section.Type: ApplicationFiled: October 18, 2019Publication date: January 6, 2022Applicant: Sony Semiconductor Solutions CorporationInventor: Hideto HASHIGUCHI
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Publication number: 20210391372Abstract: There is provided a solid-state imaging device including first, second, and third substrates stacked in this order. The first substrate includes a first semiconductor substrate and a first wiring layer. A pixel unit is formed on the first semiconductor substrate. The second substrate includes a second semiconductor substrate and a second wiring layer. The third substrate includes a third semiconductor substrate and a third wiring layer. A first coupling structure couples two of the first, second, and third substrates to each other includes a via. The via has a structure in which electrically-conductive materials are embedded in one through hole and another through hole, or a structure in which films including electrically-conductive materials are formed on inner walls of the through holes. The one through hole exposes a first wiring line in one of the wiring layers. The other through hole exposes a second wiring line in another wiring layer.Type: ApplicationFiled: August 30, 2021Publication date: December 16, 2021Applicant: SONY SEMICONDUCTOR SOLUTIONS CORPORATIONInventors: Takatoshi KAMESHIMA, Hideto HASHIGUCHI, Ikue MITSUHASHI, Hiroshi HORIKOSHI, Reijiroh SHOHJI, Minoru ISHIDA, Tadashi IIJIMA, Masaki HANEDA
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Patent number: 11201185Abstract: Provided is a solid-state imaging device including a first substrate that includes a pixel unit, a first semiconductor substrate, and a first multi-layered wiring layer stacked, a second substrate that includes circuit, a second semiconductor substrate, and a second multi-layered wiring layer stacked, the circuit having a predetermined function, a third substrate that includes a circuit, a third semiconductor substrate, and a third multi-layered wiring layer. The first substrate and the second substrate being bonded together such that the first multi-layered wiring layer is opposite to the second semiconductor substrate, and a first coupling structure for electrically coupling the circuit of the first substrate with the circuit of the second substrate, the first coupling structure is on bonding surfaces of the first substrate and the second substrate, and includes an electrode junction structure in which electrodes on the respective bonding surfaces are joined to each other in direct contact.Type: GrantFiled: March 23, 2018Date of Patent: December 14, 2021Assignee: SONY SEMICONDUCTOR SOLUTIONS CORPORATIONInventors: Ikue Mitsuhashi, Reijiroh Shohji, Minoru Ishida, Tadashi Iijima, Takatoshi Kameshima, Hideto Hashiguchi, Hiroshi Horikoshi, Masaki Haneda
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Publication number: 20210366973Abstract: Provided are a solid-state imaging device and an electronic apparatus with further improved performance. The solid-state imaging device including a first substrate on which a pixel unit is formed, and a first semiconductor substrate and a first multi-layered wiring layer are stacked, a second substrate on which a circuit having a predetermined function is formed, and a second semiconductor substrate and a second multi-layered wiring layer are stacked, and a third substrate on which a circuit having a predetermined function is formed, and a third semiconductor substrate and a third multi-layered wiring layer are stacked. The first substrate, the second substrate, and the third substrate are stacked in this order. The pixel unit has pixels arranged thereon. The first substrate and the second substrate are bonded together with the first multi-layered wiring layer and the second semiconductor substrate opposed to each other.Type: ApplicationFiled: August 9, 2021Publication date: November 25, 2021Inventors: HIROSHI HORIKOSHI, MINORU ISHIDA, REIJIROH SHOHJI, TADASHI IIJIMA, TAKATOSHI KAMESHIMA, HIDETO HASHIGUCHI, IKUE MITSUHASHI, MASAKI HANEDA
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Patent number: 11152418Abstract: There is provided a solid-state imaging device including first, second, and third substrates stacked in this order. The first substrate includes a first semiconductor substrate and a first wiring layer. A pixel unit is formed on the first semiconductor substrate. The second substrate includes a second semiconductor substrate and a second wiring layer. The third substrate includes a third semiconductor substrate and a third wiring layer. A first coupling structure couples two of the first, second, and third substrates to each other includes a via. The via has a structure in which electrically-conductive materials are embedded in one through hole and another through hole, or a structure in which films including electrically-conductive materials are formed on inner walls of the through holes. The one through hole exposes a first wiring line in one of the wiring layers. The other through hole exposes a second wiring line in another wiring layer.Type: GrantFiled: March 23, 2018Date of Patent: October 19, 2021Assignee: Sony Semiconductor Solutions CorporationInventors: Takatoshi Kameshima, Hideto Hashiguchi, Ikue Mitsuhashi, Hiroshi Horikoshi, Reijiroh Shohji, Minoru Ishida, Tadashi Iijima, Masaki Haneda