Abstract: A memory device according to the present invention includes a memory cell array including a plurality of memory cells arranged therein, the memory cell array being divided into a plurality of regions each selectable independently of the others as an object for data writing, and further includes a plurality of current supply sections provided correspondingly to the plurality of regions, respectively. Each of the plurality of current supply sections, when a corresponding region of the plurality of regions is selected as an object for data writing, is activated to supply a data write current to the corresponding region and each of the plurality of regions includes a plurality of write select lines provided correspondingly to predetermined units of the plurality of memory cells. The plurality of write select lines are selectively supplied with the data write current from a corresponding one of the plurality of current supply sections.

Abstract: Resistance elements are inserted into a main power supply line and a main ground line so that offset differential amplifiers receive voltages developed across the same. The differential amplifiers control transistors connected to a sub power supply line and a sub ground line. Thus, a leakage current flowing from the sub power supply line to the main ground line and that flowing from the main power supply line to the sub ground line are regularly kept constant. Consequently, it is possible to prevent an operation delay in an initial stage of a standby state while keeping an effect of reducing a subthreshold leakage current in a semiconductor circuit device having a hierarchical power supply structure.

Abstract: When normal bit lines BL3 and /BL3 are selected, spare bit lines SBL2 and /SBL2 are simultaneously selected, so that column select gates are placed in such a manner that these bit line pairs are connected to respective different read data bus pairs. The column select gates are distributed in placement so as not to cause a great difference in load capacitance between read data buses. A redundancy determination result is reflected on read data by activation of control signals ?1 and ?2 given immediately prior to a sense amplifier. Note that two sense amplifier may be provided with control signals ?1 and ?2 so as to select the outputs of one sense amplifier. With such a configuration adopted, it is possible to provide a memory device capable of performing high speed reading while realizing a redundancy replacement.

Abstract: A tunnel magnetic resistive element forming a magnetic memory cell includes a fixed magnetic layer having a fixed magnetic field of a fixed direction, a free magnetic layer magnetized by an applied magnetic field, and a tunnel barrier that is an insulator film provided between the fixed and free magnetic layers in a tunnel junction region. In the free magnetic layer, a region corresponding to an easy axis region having characteristics desirable as a memory cell is used as the tunnel junction region. A hard axis region having characteristics undesirable as a memory cell is not used as a portion of the tunnel magnetic resistive element.

Abstract: A P channel MOS transistor and an N channel MOS transistor turned on/off in response to an input signal in an active state as well as an N channel MOS transistor connected between an output node and the N channel MOS transistor and turned on/off in response to a control signal are provided. The input signal is at the L level in a standby state. The control signal is at the L level in the standby state and at the H level in the active state. This suppresses the effect of hot carriers in the active state and decreases a subthreshold current in the standby state.

Abstract: A driver transistor supplying a data write current to a write digit line is arranged to have its gate length direction along the same direction with a write digit line. Further, the write digit line has a reinforced portion arranged between an ordinary portion corresponding to a region where memory cells are arranged and a power supply interconnection, having interconnection cross sectional area greater than that of the ordinary portion. With this configuration, the chip area can be decreased as an increase of layout pitch of the memory cells dependent on the driver transistor size is prevented, and operational reliability can also be improved as a local increase of the current density on the write digit line is avoided.

Abstract: A main power supply line and a main ground wiring provided to supply power from one side (a first direction) of a memory region, a main power supply line and a main ground wiring provided to supply the power from the other side (a second direction opposite to the first direction) of the memory region are provided in a column direction. A bit line driver arranged on one side is supplied with power from one side, and a bit line driver arranged on the other side is supplied with the power from the other side. As a result, no current path is formed in a region of the power supply lines on the selected memory region.

Abstract: Transistors having large gate tunnel barriers are used as transistors to be on in a standby state, MIS transistors having thin gate insulating films are used as transistors to be off in the standby state, and main and sub-power supply lines and main and sub-ground lines forming a hierarchical power supply structure are isolated from each other in the standby state so that a gate tunnel current is reduced in the standby state in which a low power consumption is required. In general, a gate tunnel current reducing mechanism is provided for any circuitry operating in a standby state and an active state, and is activated in the standby state to reduce the gate tunnel current in the circuitry in the standby state, to reduce power consumption in the standby state.

Abstract: A memory device according to the present invention includes a memory cell array including a plurality of memory cells arranged therein, the memory cell array being divided into a plurality of regions each selectable independently of the others as an object for data writing, and further includes a plurality of current supply sections provided correspondingly to the plurality of regions, respectively. Each of the plurality of current supply sections, when a corresponding region of the plurality of regions is selected as an object for data writing, is activated to supply a data write current to the corresponding region and each of the plurality of regions includes a plurality of write select lines provided correspondingly to predetermined units of the plurality of memory cells. The plurality of write select lines are selectively supplied with the data write current from a corresponding one of the plurality of current supply sections.

Abstract: In the data read operation, a memory cell and a dummy memory cell are respectively coupled to two bit lines of a selected bit line pair, and a data read current is supplied thereto. In the selected memory cell column, a read gate drives the respective voltages on a read data bus pair, according to the respective voltages on the bit lines. A data read circuit amplifies the voltage difference between the read data buses so as to output read data. The use of the read gate enables the read data buses to be disconnected from a data read current path. As a result, respective voltage changes on the bit lines are rapidly produced, whereby the data read speed can be increased.

Abstract: In read operation, a current from a current supply transistor flows through a selected memory cell and a data line. Moreover, a bias magnetic field having such a level that does not destroy storage data is applied to the selected memory cell. By application of the bias magnetic field, an electric resistance of the selected memory cell changes in the positive or negative direction depending on the storage data level. A sense amplifier amplifies the difference between voltages on the data line before and after the change in electric resistance of the selected memory cell. Data is thus read from the selected memory cell by merely accessing the selected memory cell. Moreover, since the data line and the sense amplifier are insulated from each other by a capacitor, the sense amplifier can be operated in an optimal input voltage range regardless of magnetization characteristics of the memory cells.

Abstract: Normal memory cells are arranged in rows and columns, and dummy memory cells are arranged to form dummy memory cell rows by sharing memory cell columns with the normal memory cells. When there is at least one defect in the normal memory cells and/or the dummy memory cells, replacement/repair is carried out using a redundant column in a unit of memory cell column. The redundant column includes not only spare memory cells for repair of the normal memory cells but also spare dummy memory cells for repair of the dummy memory cells.

Abstract: A tunneling magneto-resistance element forming an MTJ memory cell has an elongated form having an aspect ratio larger than one for stabilizing the magnetization characteristics. Bit lines and write word lines for carrying data write currents are arranged along short and long sides of the tunneling magneto-resistance element, respectively. The data write current flowing through the bit line, which can easily have an interconnection width, is designed to be larger than the data write current flowing through the write word line. For example, a distance between the write word line and the tunneling magneto-resistance element is smaller than a distance between the bit line and the tunneling magneto-resistance element.

Abstract: A program element has a magnetic layer electrically connected between first and second nodes. At least a portion of the magnetic layer forms a link portion designed to be blown with external laser irradiation. The magnetic layer is provided in the same layer as and with the same structure as a tunneling magneto-resistance element in an MTJ memory cell. An electrical contact between the magnetic layer and respective one of the first and second nodes has the same structure as the electrical contact between the tunneling magneto-resistance element and an interconnection provided in the same metal interconnection layer as respective one of the first and second nodes in the MTJ memory cell.

Abstract: A memory device according to the present invention includes a memory cell array including a plurality of memory cells arranged therein, the memory cell array being divided into a plurality of regions each selectable independently of the others as an object for data writing, and further includes a plurality of current supply sections provided correspondingly to the plurality of regions, respectively. Each of the plurality of current supply sections, when a corresponding region of the plurality of regions is selected as an object for data writing, is activated to supply a data write current to the corresponding region and each of the plurality of regions includes a plurality of write select lines provided correspondingly to predetermined units of the plurality of memory cells. The plurality of write select lines are selectively supplied with the data write current from a corresponding one of the plurality of current supply sections.

Abstract: When normal bit lines BL3 and /BL3 are selected, spare bit lines SBL2 and /SBL2 are simultaneously selected, so that column select gates are placed in such a manner that these bit line pairs are connected to respective different read data bus pairs. The column select gates are distributed in placement so as not to cause a great difference in load capacitance between read data buses. A redundancy determination result is reflected on read data by activation of control signals ?1 and ?2 given immediately prior to a sense amplifier. Note that two sense amplifier may be provided with control signals ?1 and ?2 so as to select the outputs of one sense amplifier. With such a configuration adopted, it is possible to provide a memory device capable of performing high speed reading while realizing a redundancy replacement.

Abstract: A tunneling magneto-resistance element forming an MTJ memory cell has an elongated form having an aspect ratio larger than one for stabilizing the magnetization characteristics. Bit lines and write word lines for carrying data write currents are arranged along short and long sides of the tunneling magneto-resistance element, respectively. The data write current flowing through the bit line, which can easily have an interconnection width, is designed to be larger than the data write current flowing through the write word line. For example, a distance between the write word line and the tunneling magneto-resistance element is smaller than a distance between the bit line and the tunneling magneto-resistance element.

Abstract: Capacitors are provided for changing the voltage level of data lines, respectively, in a data reading operation. A signal line electrically coupled to capacitors is provided. Capacitors charge data lines in accordance with the voltage level of signal line by capacitive coupling. Thus, data lines can be charged quickly to achieve a fast data reading operation.

Abstract: A P channel MOS transistor and an N channel MOS transistor turned on/off in response to an input signal in an active state as well as an N channel MOS transistor connected between an output node and the N channel MOS transistor and turned on/off in response to a control signal are provided. The input signal is at the L level in a standby state. The control signal is at the L level in the standby state and at the H level in the active state. This suppresses the effect of hot carriers in the active state and decreases a subthreshold current in the standby state.

Abstract: An internal power supply potential generation circuit includes an overcharge prevention circuit connected to an internal power supply node. The overcharge prevention circuit includes a circuit outputting a signal to be determined that is determined by an internal power supply potential, a differential amplification circuit amplifying a difference in potential between the signal to be determined and a reference potential for output to a node as a signal indicating that current should be drawn, and a current draw circuit drawing current from the internal power supply node in response to the signal indicating that current should be drawn. Thus the semiconductor integrated circuit device of interest can provide a steady internal power supply potential.