Patents by Inventor Hideto Hidaka

Hideto Hidaka has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Thin film magnetic memory device having a magnetic tunnel junction
    Publication number: 20050083773
    Abstract: Bit lines and source lines are precharged to a power supply voltage before data read operation. In the data read operation, a corresponding bit line is coupled to a data bus as well as a corresponding source line is driven to a ground voltage only in the selected memory cell column. In the non-selected memory cell columns, the bit lines and the source lines are retained at the precharge voltage, i.e., the power supply voltage. No charging/discharging current is produced in the bit lines of the non-selected memory cell columns, that is, a charging/discharging current that does not directly contribute the data read operation is not produced, thereby allowing for reduction in power consumption in the data read operation.
    Type: Application
    Filed: November 8, 2004
    Publication date: April 21, 2005
    Applicant: RENESAS TECHNOLOGY CORP.
    Inventor: Hideto Hidaka
  • Thin-film magnetic memory device executing data writing with data write magnetic fields in two directions
    Publication number: 20050083770
    Abstract: A tunneling magneto-resistance element forming an MTJ memory cell has an elongated form having an aspect ratio larger than one for stabilizing the magnetization characteristics. Bit lines and write word lines for carrying data write currents are arranged along short and long sides of the tunneling magneto-resistance element, respectively. The data write current flowing through the bit line, which can easily have an interconnection width, is designed to be larger than the data write current flowing through the write word line. For example, a distance between the write word line and the tunneling magneto-resistance element is smaller than a distance between the bit line and the tunneling magneto-resistance element.
    Type: Application
    Filed: October 5, 2004
    Publication date: April 21, 2005
    Applicant: RENESAS TECHNOLOGY CORP.
    Inventor: Hideto Hidaka
  • Thin film magnetic memory device having a magnetic tunnel junction
    Patent number: 6876575
    Abstract: Bit lines and source lines are precharged to a power supply voltage before data read operation. In the data read operation, a corresponding bit line is coupled to a data bus as well as a corresponding source line is driven to a ground voltage only in the selected memory cell column. In the non-selected memory cell columns, the bit lines and the source lines are retained at the precharge voltage, i.e., the power supply voltage. No charging/discharging current is produced in the bit lines of the non-selected memory cell columns, that is, a charging/discharging current that does not directly contribute the data read operation is not produced, thereby allowing for reduction in power consumption in the data read operation.
    Type: Grant
    Filed: October 22, 2001
    Date of Patent: April 5, 2005
    Assignee: Renesas Technology Corp.
    Inventor: Hideto Hidaka
  • Thin film magnetic memory device having redundant configuration
    Patent number: 6876576
    Abstract: Normal memory cells are arranged in rows and columns, and dummy memory cells are arranged to form dummy memory cell rows by sharing memory cell columns with the normal memory cells. When there is at least one defect in the normal memory cells and/or the dummy memory cells, replacement/repair is carried out using a redundant column in a unit of memory cell column. The redundant column includes not only spare memory cells for repair of the normal memory cells but also spare dummy memory cells for repair of the dummy memory cells.
    Type: Grant
    Filed: December 11, 2002
    Date of Patent: April 5, 2005
    Assignee: Renesas Technology Corp.
    Inventor: Hideto Hidaka
  • Thin film magnetic memory device applying a magnetic field to write data
    Patent number: 6870757
    Abstract: Each write word line has one end connected by a write drive circuit to a power supply voltage selectively and the other end to a ground voltage. The write drive circuit is staggered in arrangement and thus connected to either one or the other end of each write word line. A write drive circuit has a first transistor and a second transistor. When a memory cell row corresponding to the write drive circuit is selected the first transistor connects a corresponding write word line to the power supply voltage to supply a data writing current and when an adjacent row is selected the transistor connects the corresponding write word line to the power supply voltage. The second transistor passes a magnetic field canceling current, which cancels a magnetic field leaking from a data writing current of an adjacent row.
    Type: Grant
    Filed: August 26, 2002
    Date of Patent: March 22, 2005
    Assignee: Renesas Technology Corp.
    Inventor: Hideto Hidaka
  • Thin film magnetic memory device suppressing resistance of transistors present in current path
    Patent number: 6868004
    Abstract: An access transistor ATR in an MTJ memory cell, which is one of transistors connected to a read current path, is constituted with a surface-channel, field-effect transistor. The surface-channel, field-effect transistor has a channel resistance lower than a channel-embedded, field-effect transistor, and can reduce an RC load in the read current path. Accordingly, data can be read with a high speed.
    Type: Grant
    Filed: March 11, 2003
    Date of Patent: March 15, 2005
    Assignee: Renesas Technology Corp.
    Inventors: Hideto Hidaka, Masatoshi Ishikawa, Tsukasa Ooishi
  • Thin film magnetic memory device provided with magnetic tunnel junctions
    Patent number: 6868005
    Abstract: A driver transistor supplying a data write current to a write digit line is arranged to have its gate length direction along the same direction with a write digit line. Further, the write digit line has a reinforced portion arranged between an ordinary portion corresponding to a region where memory cells are arranged and a power supply interconnection, having interconnection cross sectional area greater than that of the ordinary portion. With this configuration, the chip area can be decreased as an increase of layout pitch of the memory cells dependent on the driver transistor size is prevented, and operational reliability can also be improved as a local increase of the current density on the write digit line is avoided.
    Type: Grant
    Filed: May 20, 2003
    Date of Patent: March 15, 2005
    Assignee: Renesas Technology Corp.
    Inventor: Hideto Hidaka
  • Semiconductor device with reduced current consumption in standby state
    Patent number: 6868029
    Abstract: A logic portion outputs to a DRAM portion a start address and an end address indicating a memory region where data to be stored is present prior to transition to power down mode having reduced current consumption. In the power down mode, a refresh control unit holds the start address and the end address and controls refresh to be carried out for data only in a region requiring refresh. The power supply of the logic portion is set in off state in the power down mode and accordingly a semiconductor device can consume reduced current while holding data.
    Type: Grant
    Filed: June 27, 2003
    Date of Patent: March 15, 2005
    Assignee: Renesas Technology Corp.
    Inventors: Tsukasa Ooishi, Takaharu Tsuji, Masatoshi Ishikawa, Hideto Hidaka, Hiroshi Kato
  • Thin film magnetic memory device suppressing internal magnetic noises
    Publication number: 20050052929
    Abstract: A write drive circuit provided for every write word line supplies a data write current to a write word line of a selected row, and supplies a magnetic-field canceling current to a write word line of an adjacent row in the opposite direction to that of the data write current. In each write drive circuit, the data write current is supplied in response to turning-ON of first and second driver transistors, and the magnetic-field canceling current is supplied in response to turning-ON of the second driver transistor.
    Type: Application
    Filed: October 7, 2004
    Publication date: March 10, 2005
    Inventor: Hideto Hidaka
  • Thin film magnetic memory device having a redundant structure
    Patent number: 6865103
    Abstract: In data write operation, a data write current starts being supplied to a write word line of the selected row at a first time without waiting for redundant determination. A data write current starts being supplied to a bit line or sub bit line of the selected column at a second time that is later than the first time according to the redundant determination result. The redundant determination is conducted between the first and second times. The data write currents flowing through the write word line and the bit line generate magnetic fields of the hard-axis and easy-axis directions for the selected memory sell, respectively.
    Type: Grant
    Filed: May 24, 2002
    Date of Patent: March 8, 2005
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventor: Hideto Hidaka
  • Thin film magnetic memory device with magnetic tunnel junction
    Patent number: 6862209
    Abstract: An access transistor in an MTJ memory cell, which is one of transistors connected to a read current path, is fabricated with a semiconductor layer formed on an insulating film on a semiconductor substrate SUB, and includes impurity regions, a gate region and a body region. That is, the access transistor is fabricated with an SOI (Silicon On Insulator) structure in order to reduce an off-leak current.
    Type: Grant
    Filed: February 11, 2003
    Date of Patent: March 1, 2005
    Assignee: Renesas Technology Corp.
    Inventors: Hideto Hidaka, Masatoshi Ishikawa, Tsukasa Ooishi
  • Semiconductor memory device capable of overcoming refresh disturb
    Patent number: 6859403
    Abstract: Drains of first and second transistors are connected to a low level line of an internal circuitry such as a sense amplifier related to determination of a potential in a memory cell. The first transistor has its gate diode-connected to a sense drive line and its source grounded. The second transistor receives at its gate an internally generated signal, and its source is grounded. In the standby state, the potential of the sense drive line is set higher than low level of said word lines by the threshold voltage Vthn of the first transistor and used as dummy GND potential Vss?, and in the active state, the second transistor is rendered conductive so as to prevent floating of the sense drive line from the dummy GND potential Vss?.
    Type: Grant
    Filed: April 2, 2004
    Date of Patent: February 22, 2005
    Assignee: Renesas Technology Corp.
    Inventors: Hideto Hidaka, Mikio Asakura, Kazuyasu Fujishima, Tsukasa Ooishi, Kazutami Arimoto, Shigeki Tomishima, Masaki Tsukude
  • Thin film magnetic memory device suppressing internal magnetic noises
    Patent number: 6856538
    Abstract: A write drive circuit provided for every write word line supplies a data write current to a write word line of a selected row, and supplies a magnetic-field canceling current to a write word line of an adjacent row in the opposite direction to that of the data write current. In each write drive circuit, the data write current is supplied in response to turning-ON of first and second driver transistors, and the magnetic-field canceling current is supplied in response to turning-ON of the second driver transistor.
    Type: Grant
    Filed: December 26, 2002
    Date of Patent: February 15, 2005
    Assignee: Renesas Technology Corp.
    Inventor: Hideto Hidaka
  • Thin film magnetic memory device conducting read operation by a self-reference method
    Patent number: 6856565
    Abstract: In read operation, a current from a current supply transistor flows through a selected memory cell and a data line. Moreover, a bias magnetic field having such a level that does not destroy storage data is applied to the selected memory cell. By application of the bias magnetic field, an electric resistance of the selected memory cell changes in the positive or negative direction depending on the storage data level. A sense amplifier amplifies the difference between voltages on the data line before and after the change in electric resistance of the selected memory cell. Data is thus read from the selected memory cell by merely accessing the selected memory cell. Moreover, since the data line and the sense amplifier are insulated from each other by a capacitor, the sense amplifier can be operated in an optimal input voltage range regardless of magnetization characteristics of the memory cells.
    Type: Grant
    Filed: December 20, 2002
    Date of Patent: February 15, 2005
    Assignee: Renesas Technology Corp.
    Inventors: Tsukasa Ooishi, Hideto Hidaka
  • Thin film magnetic memory device including memory cells having a magnetic tunnel junction
    Patent number: 6856539
    Abstract: In the data read operation, a memory cell and a dummy memory cell are respectively coupled to two bit lines of a selected bit line pair, and a data read current is supplied thereto. In the selected memory cell column, a read gate drives the respective voltages on a read data bus pair, according to the respective voltages on the bit lines. A data read circuit amplifies the voltage difference between the read data buses so as to output read data. The use of the read gate enables the read data buses to be disconnected from a data read current path. As a result, respective voltage changes on the bit lines are rapidly produced, whereby the data read speed can be increased.
    Type: Grant
    Filed: June 2, 2004
    Date of Patent: February 15, 2005
    Assignee: Renesas Technology Corp.
    Inventor: Hideto Hidaka
  • Thin film magnetic memory device conducting data write operation by application of a magnetic field
    Publication number: 20050030829
    Abstract: A peripheral circuitry is provided adjacent to a memory array and conducts read and write operations from and to the memory array. A power supply voltage line and a ground line for supplying an operating voltage to the peripheral circuitry supply a power supply voltage and a ground voltage, respectively. The power supply voltage line and the ground line are arranged so that a magnetic field generated by a current flowing through the power supply voltage line and a magnetic field generated by a current flowing through the ground line cancel each other in the memory array.
    Type: Application
    Filed: September 14, 2004
    Publication date: February 10, 2005
    Applicant: Renesas Technology Corp.
    Inventor: Hideto Hidaka
  • Thin film magnetic memory device reducing a charging time of a data line in a data read operation
    Publication number: 20050024935
    Abstract: During data reading, a sense enable signal is activated to start charging of a data line prior to formation of a current path including the data line and a selected memory cell in accordance with row and column selecting operations. Charging of the data line is completed early so that it is possible to reduce a time required from start of the data reading to such a state that a passing current difference between the data lines reaches a level corresponding to storage data of the selected memory cell, and the data reading can be performed fast.
    Type: Application
    Filed: September 2, 2004
    Publication date: February 3, 2005
    Applicants: MITSUBISHI DENKI KABUSHIKI KAISHA, MITSUBISHI ELECTRIC ENGINEERING COMPANY LIMITED
    Inventors: Hiroaki Tanizaki, Hideto Hidaka, Tsukasa Ooishi
  • Semiconductor test device for conducting an operation test in parallel on many chips in a wafer test and semiconductor test method
    Patent number: 6845477
    Abstract: A plurality of test target chips on a test target wafer are simultaneously and electrically coupled to a plurality of chips on a test wafer via a wafer contactor. Each chip on the test wafer has a test circuit for conducting an operation test on each chip on the test target wafer. Since the test circuit is in a one-to-one relationship with respect to the test target chip, and is arranged on the test wafer other than the test target wafer, the many chips can be simultaneously tested in parallel during the wafer test without increasing an area of the test target chips.
    Type: Grant
    Filed: March 7, 2001
    Date of Patent: January 18, 2005
    Assignee: Renesas Technology Corp.
    Inventors: Hideto Hidaka, Tsukasa Ooishi
  • Semiconductor memory device with current driver providing bi-directional current to data write line
    Publication number: 20050007834
    Abstract: First and second current drivers are connected to one end of corresponding first and second write bit lines, respectively, and the first and second write bit lines are directly connected, at the other end, to a common line. The first and second current drivers receive a first power supply voltage and the ground voltage, while the common line receives a second power supply voltage higher than the ground voltage and lower than the first power supply voltage. The first and second current drivers cause a current for data writing to flow in a first direction based on a voltage difference between the first power supply voltage and the second power supply voltage, and cause a current for data writing to flow in a second direction based on a voltage difference between the second power supply voltage and the ground voltage.
    Type: Application
    Filed: July 8, 2004
    Publication date: January 13, 2005
    Inventor: Hideto Hidaka
  • Semiconductor device having mechanism capable of high-speed operation
    Publication number: 20050007862
    Abstract: A semiconductor device comprises a memory cell block and a sense amplifier zone. A selection gate included in the sense amplifier zone is turned on for selectively coupling the memory cell block with the sense amplifier zone. Local drivers are dispersively arranged on a BLI wire transmitting a gate control signal, and a driver is arranged on an end of the BLI wire. The driver pulls down the potential of the BLI wire at a high speed.
    Type: Application
    Filed: July 27, 2004
    Publication date: January 13, 2005
    Applicant: RENESAS TECHNOLOGY CORP.
    Inventor: Hideto Hidaka