Patents by Inventor Hideto Ohnuma

Hideto Ohnuma has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240016044
    Abstract: As a result of miniaturization of a pixel region associated with an improvement in definition and an increase in a substrate size associated with an increase in area, defects due to precision, bending, and the like of a mask used at the time of evaporation have become issues. A partition including portions with different thicknesses over a pixel electrode (also referred to as a first electrode) in a display region and in the vicinity of a pixel electrode layer is formed, without increasing the number of steps, by using a photomask or a reticle provided with an auxiliary pattern having a light intensity reduction function made of a diffraction grating pattern or a semi-transmissive film.
    Type: Application
    Filed: September 20, 2023
    Publication date: January 11, 2024
    Applicant: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Hideaki Kuwabara, Hideto Ohnuma
  • Patent number: 11770965
    Abstract: As a result of miniaturization of a pixel region associated with an improvement in definition and an increase in a substrate size associated with an increase in area, defects due to precision, bending, and the like of a mask used at the lime of evaporation have become issues. A partition including portions with different thicknesses over a pixel electrode (also referred to as a first electrode) in a display region and in the vicinity of a pixel electrode layer is formed, without increasing the number of steps, by using a photomask or a reticle provided with an auxiliary pattern having a light intensity reduction function made of a diffraction grating pattern or a semi-transmissive film.
    Type: Grant
    Filed: November 4, 2021
    Date of Patent: September 26, 2023
    Inventors: Hideaki Kuwabara, Hideto Ohnuma
  • Publication number: 20220059809
    Abstract: As a result of miniaturization of a pixel region associated with an improvement in definition and an increase in a substrate size associated with an increase in area, defects due to precision, bending, and the like of a mask used at the lime of evaporation have become issues. A partition including portions with different thicknesses over a pixel electrode (also referred to as a first electrode) in a display region and in the vicinity of a pixel electrode layer is formed, without increasing the number of steps, by using a photomask or a reticle provided with an auxiliary pattern having a light intensity reduction function made of a diffraction grating pattern or a semi-transmissive film.
    Type: Application
    Filed: November 4, 2021
    Publication date: February 24, 2022
    Applicant: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Hideaki Kuwabara, Hideto Ohnuma
  • Patent number: 11171315
    Abstract: As a result of miniaturization of a pixel region associated with an improvement in definition and an increase in a substrate size associated with an increase in area, defects due to precision, bending, and the like of a mask used at the time of evaporation have become issues. A partition including portions with different thicknesses over a pixel electrode (also referred to as a first electrode) in a display region and in the vicinity of a pixel electrode layer is formed, without increasing the number of steps, by using a photomask or a reticle provided with an auxiliary pattern having a light intensity reduction function made of a diffraction grating pattern or a semi-transmissive film.
    Type: Grant
    Filed: February 1, 2019
    Date of Patent: November 9, 2021
    Inventors: Hideaki Kuwabara, Hideto Ohnuma
  • Publication number: 20190165334
    Abstract: As a result of miniaturization of a pixel region associated with an improvement in definition and an increase in a substrate size associated with an increase in area, defects due to precision, bending, and the like of a mask used at the time of evaporation have become issues. A partition including portions with different thicknesses over a pixel electrode (also referred to as a first electrode) in a display region and in the vicinity of a pixel electrode layer is formed, without increasing the number of steps, by using a photomask or a reticle provided with an auxiliary pattern having a light intensity reduction function made of a diffraction grating pattern or a semi-transmissive film.
    Type: Application
    Filed: February 1, 2019
    Publication date: May 30, 2019
    Applicant: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Hideaki KUWABARA, Hideto OHNUMA
  • Patent number: 10199612
    Abstract: As a result of miniaturization of a pixel region associated with an improvement in definition and an increase in a substrate size associated with an increase in area, defects due to precision, bending, and the like of a mask used at the time of evaporation have become issues. A partition including portions with different thicknesses over a pixel electrode (also referred to as a first electrode) in a display region and in the vicinity of a pixel electrode layer is formed, without increasing the number of steps, by using a photomask or a reticle provided with an auxiliary pattern having a light intensity reduction function made of a diffraction grating pattern or a semi-transmissive film.
    Type: Grant
    Filed: February 7, 2018
    Date of Patent: February 5, 2019
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Hideaki Kuwabara, Hideto Ohnuma
  • Publication number: 20180183016
    Abstract: As a result of miniaturization of a pixel region associated with an improvement in definition and an increase in a substrate size associated with an increase in area, defects due to precision, bending, and the like of a mask used at the time of evaporation have become issues. A partition including portions with different thicknesses over a pixel electrode (also referred to as a first electrode) in a display region and in the vicinity of a pixel electrode layer is formed, without increasing the number of steps, by using a photomask or a reticle provided with an auxiliary pattern having a light intensity reduction function made of a diffraction grating pattern or a semi-transmissive film.
    Type: Application
    Filed: February 7, 2018
    Publication date: June 28, 2018
    Applicant: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Hideaki Kuwabara, Hideto OHNUMA
  • Patent number: 9991290
    Abstract: It is an object of the present invention to provide a method for preventing a breaking and poor contact, without increasing the number of steps, thereby forming an integrated circuit with high driving performance and reliability. The present invention applies a photo mask or a reticle each of which is provided with a diffraction grating pattern or with an auxiliary pattern formed of a semi-translucent film having a light intensity reducing function to a photolithography step for forming wires in an overlapping portion of wires. And a conductive film to serve as a lower wire of a two-layer structure is formed, and then, a resist pattern is formed so that a first layer of the lower wire and a second layer narrower than the first layer are formed for relieving a steep step.
    Type: Grant
    Filed: February 8, 2017
    Date of Patent: June 5, 2018
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Masayuki Sakakura, Hideto Ohnuma, Hideaki Kuwabara
  • Patent number: 9966560
    Abstract: A highly reliable light-emitting module or light-emitting device is provided. A method for manufacturing a highly reliable light-emitting module is provided. The light-emitting module includes, between a first substrate and a second substrate, a first electrode provided over the first substrate, a second electrode provided over the first electrode with a layer containing a light-emitting organic compound interposed therebetween, and a sacrifice layer formed using a liquid material provided over the second electrode.
    Type: Grant
    Filed: April 17, 2015
    Date of Patent: May 8, 2018
    Assignee: Semiconductor Energy Laboratory Co., LTD.
    Inventors: Shunpei Yamazaki, Satoshi Seo, Hideto Ohnuma, Hajime Kimura, Yasuhiro Jinbo
  • Patent number: 9917274
    Abstract: To provide a light-emitting panel in which the occurrence of crosstalk is suppressed. To provide a method for manufacturing a light-emitting panel in which the occurrence of crosstalk is suppressed. The light-emitting panel includes a first electrode of one light-emitting element, a first electrode of the other light-emitting element, and an insulating partition which separates the two first electrodes. A portion with a thickness A1 smaller than a thickness A0 of a portion of the layer containing a light-emitting organic compound, which overlaps with a side surface of the partition, is included. The ratio (B1/B0) of a thickness B1 of a portion of the second electrode, which overlaps with a side surface of the partition, to a thickness B0 of a portion of the second electrode, which overlaps with the first electrode, is higher than the ratio (A1/A0).
    Type: Grant
    Filed: November 15, 2016
    Date of Patent: March 13, 2018
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Hideto Ohnuma, Noriko Miyairi, Naoyuki Senda
  • Patent number: 9910334
    Abstract: This invention provides a semiconductor device having high operation performance and high reliability. An LDD region 707 overlapping with a gate wiring is arranged in an n-channel TFT 802 forming a driving circuit, and a TFT structure highly resistant to hot carrier injection is achieved. LDD regions 717, 718, 719 and 720 not overlapping with a gate wiring are arranged in an n-channel TFT 804 forming a pixel unit. As a result, a TFT structure having a small OFF current value is achieved. In this instance, an element belonging to the Group 15 of the Periodic Table exists in a higher concentration in the LDD region 707 than in the LDD regions 717, 718, 719 and 720.
    Type: Grant
    Filed: August 26, 2016
    Date of Patent: March 6, 2018
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Satoshi Murakami, Jun Koyama, Yukio Tanaka, Hidehito Kitakado, Hideto Ohnuma
  • Patent number: 9893325
    Abstract: As a result of miniaturization of a pixel region associated with an improvement in definition and an increase in a substrate size associated with an increase in area, defects due to precision, bending, and the like of a mask used at the time of evaporation have become issues. A partition including portions with different thicknesses over a pixel electrode (also referred to as a first electrode) in a display region and in the vicinity of a pixel electrode layer is formed, without increasing the number of steps, by using a photomask or a reticle provided with an auxiliary pattern having a light intensity reduction function made of a diffraction grating pattern or a semi-transmissive film.
    Type: Grant
    Filed: December 28, 2016
    Date of Patent: February 13, 2018
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Hideaki Kuwabara, Hideto Ohnuma
  • Patent number: 9812217
    Abstract: Disclosed is a driver circuit including a latch circuit, a shift register circuit, and a switching circuit, where the latch circuit is provided over the shift register circuit and the switching circuit. The shift register circuit and the switching circuit may have a silicon-based semiconductor, while the latch circuit may have an oxide semiconductor. The latch circuit includes a first transistor and a second transistor connected in series. The latch circuit may further include a first capacitor and a second capacitor which are electrically connected to the first transistor and the second transistor. A display device using the driver circuit as well as a method for preparing the driver circuit is also disclosed.
    Type: Grant
    Filed: April 6, 2016
    Date of Patent: November 7, 2017
    Assignee: Semiconductor Energy Laboratory Co., LTD.
    Inventors: Shunpei Yamazaki, Hideto Ohnuma, Kei Takahashi
  • Publication number: 20170148827
    Abstract: It is an object of the present invention to provide a method for preventing a breaking and poor contact, without increasing the number of steps, thereby forming an integrated circuit with high driving performance and reliability. The present invention applies a photo mask or a reticle each of which is provided with a diffraction grating pattern or with an auxiliary pattern formed of a semi-translucent film having a light intensity reducing function to a photolithography step for forming wires in an overlapping portion of wires. And a conductive film to serve as a lower wire of a two-layer structure is formed, and then, a resist pattern is formed so that a first layer of the lower wire and a second layer narrower than the first layer are formed for relieving a steep step.
    Type: Application
    Filed: February 8, 2017
    Publication date: May 25, 2017
    Inventors: Masayuki SAKAKURA, Hideto OHNUMA, Hideaki KUWABARA
  • Publication number: 20170110692
    Abstract: As a result of miniaturization of a pixel region associated with an improvement in definition and an increase in a substrate size associated with an increase in area, defects due to precision, bending, and the like of a mask used at the time of evaporation have become issues. A partition including portions with different thicknesses over a pixel electrode (also referred to as a first electrode) in a display region and in the vicinity of a pixel electrode layer is formed, without increasing the number of steps, by using a photomask or a reticle provided with an auxiliary pattern having a light intensity reduction function made of a diffraction grating pattern or a semi-transmissive film.
    Type: Application
    Filed: December 28, 2016
    Publication date: April 20, 2017
    Applicant: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Hideaki Kuwabara, Hideto Ohnuma
  • Publication number: 20170062754
    Abstract: To provide a light-emitting panel in which the occurrence of crosstalk is suppressed. To provide a method for manufacturing a light-emitting panel in which the occurrence of crosstalk is suppressed. The light-emitting panel includes a first electrode of one light-emitting element, a first electrode of the other light-emitting element, and an insulating partition which separates the two first electrodes. A portion with a thickness A1 smaller than a thickness A0 of a portion of the layer containing a light-emitting organic compound, which overlaps with a side surface of the partition, is included. The ratio (B1/B0) of a thickness B1 of a portion of the second electrode, which overlaps with a side surface of the partition, to a thickness B0 of a portion of the second electrode, which overlaps with the first electrode, is higher than the ratio (A1/A0).
    Type: Application
    Filed: November 15, 2016
    Publication date: March 2, 2017
    Applicant: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Hideto Ohnuma, Noriko MIYAIRI, Naoyuki SENDA
  • Publication number: 20170052398
    Abstract: This invention provides a semiconductor device having high operation performance and high reliability. An LDD region 707 overlapping with a gate wiring is arranged in an n-channel TFT 802 forming a driving circuit, and a TFT structure highly resistant to hot carrier injection is achieved. LDD regions 717, 718, 719 and 720 not overlapping with a gate wiring are arranged in an n-channel TFT 804 forming a pixel unit. As a result, a TFT structure having a small OFF current value is achieved. In this instance, an element belonging to the Group 15 of the Periodic Table exists in a higher concentration in the LDD region 707 than in the LDD regions 717, 718, 719 and 720.
    Type: Application
    Filed: August 26, 2016
    Publication date: February 23, 2017
    Applicant: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei YAMAZAKI, Satoshi MURAKAMI, Jun KOYAMA, Yukio TANAKA, Hidehito KITAKADO, Hideto OHNUMA
  • Patent number: 9576986
    Abstract: It is an object of the present invention to provide a method for preventing a breaking and poor contact, without increasing the number of steps, thereby forming an integrated circuit with high driving performance and reliability. The present invention applies a photo mask or a reticle each of which is provided with a diffraction grating pattern or with an auxiliary pattern formed of a semi-translucent film having a light intensity reducing function to a photolithography step for forming wires in an overlapping portion of wires. And a conductive film to serve as a lower wire of a two-layer structure is formed, and then, a resist pattern is formed so that a first layer of the lower wire and a second layer narrower than the first layer are formed for relieving a steep step.
    Type: Grant
    Filed: July 25, 2014
    Date of Patent: February 21, 2017
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Masayuki Sakakura, Hideto Ohnuma, Hideaki Kuwabara
  • Patent number: 9536774
    Abstract: An SOI substrate having an SOI layer that can be used in practical applications even when a substrate with low upper temperature limit, such as a glass substrate, is used, is provided. A semiconductor device using such an SOI substrate, is provided. In bonding a single-crystal semiconductor layer to a substrate having an insulating surface or an insulating substrate, a silicon oxide film formed using organic silane as a material on one or both surfaces that are to form a bond is used. According to the present invention, a substrate with an upper temperature limit of 700° C. or lower, such as a glass substrate, can be used, and an SOI layer that is strongly bonded to the substrate can be obtained. In other words, a single-crystal semiconductor layer can be formed over a large-area substrate that is longer than one meter on each side.
    Type: Grant
    Filed: July 21, 2014
    Date of Patent: January 3, 2017
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Hideto Ohnuma, Tetsuya Kakehata, Yoichi Iikubo
  • Patent number: 9536932
    Abstract: As a result of miniaturization of a pixel region associated with an improvement in definition and an increase in a substrate size associated with an increase in area, defects due to precision, bending, and the like of a mask used at the time of evaporation have become issues. A partition including portions with different thicknesses over a pixel electrode (also referred to as a first electrode) in a display region and in the vicinity of a pixel electrode layer is formed, without increasing the number of steps, by using a photomask or a reticle provided with an auxiliary pattern having a light intensity reduction function made of a diffraction grating pattern or a semi-transmissive film.
    Type: Grant
    Filed: December 23, 2015
    Date of Patent: January 3, 2017
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Hideaki Kuwabara, Hideto Ohnuma