Patents by Inventor Hideto Ohnuma
Hideto Ohnuma has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 8884371Abstract: An object is to provide an SOI substrate provided with a semiconductor layer which can be used practically even when a glass substrate is used as a base substrate. Another object is to provide a semiconductor device having high reliability using such an SOI substrate. An altered layer is formed on at least one surface of a glass substrate used as a base substrate of an SOI substrate to form the SOI substrate. The altered layer is formed on at least the one surface of the glass substrate by cleaning the glass substrate with solution including hydrochloric acid, sulfuric acid or nitric acid. The altered layer has a higher proportion of silicon oxide in its composition and a lower density than the glass substrate.Type: GrantFiled: December 19, 2013Date of Patent: November 11, 2014Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventors: Tetsuya Kakehata, Hideto Ohnuma, Yoshiaki Yamamoto, Kenichiro Makino
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Publication number: 20140329371Abstract: An SOI substrate having an SOI layer that can be used in practical applications even when a substrate with low upper temperature limit, such as a glass substrate, is used, is provided. A semiconductor device using such an SOI substrate, is provided. In bonding a single-crystal semiconductor layer to a substrate having an insulating surface or an insulating substrate, a silicon oxide film formed using organic silane as a material on one or both surfaces that are to form a bond is used. According to the present invention, a substrate with an upper temperature limit of 700° C. or lower, such as a glass substrate, can be used, and an SOI layer that is strongly bonded to the substrate can be obtained. In other words, a single-crystal semiconductor layer can be formed over a large-area substrate that is longer than one meter on each side.Type: ApplicationFiled: July 21, 2014Publication date: November 6, 2014Inventors: Hideto OHNUMA, Tetsuya KAKEHATA, Yoichi IIKUBO
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Patent number: 8847483Abstract: As a result of miniaturization of a pixel region associated with an improvement in definition and an increase in a substrate size associated with an increase in area, defects due to precision, bending, and the like of a mask used at the time of evaporation have become issues. A partition including portions with different thicknesses over a pixel electrode (also referred to as a first electrode) in a display region and in the vicinity of a pixel electrode layer is formed, without increasing the number of steps, by using a photomask or a reticle provided with an auxiliary pattern having a light intensity reduction function made of a diffraction grating pattern or a semi-transmissive film.Type: GrantFiled: May 13, 2013Date of Patent: September 30, 2014Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventors: Hideaki Kuwabara, Hideto Ohnuma
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Publication number: 20140256096Abstract: A semiconductor device is provided, which includes a single crystal semiconductor layer formed over an insulating surface and having a source region, a drain region, and a channel formation region, a gate insulating film covering the single crystal semiconductor layer and a gate electrode overlapping with the channel formation region with the gate insulating film interposed therebetween. In the semiconductor device, at least the drain region of the source and drain regions includes a first impurity region adjacent to the channel formation region and a second impurity region adjacent to the first impurity region. A maximum of an impurity concentration distribution in the first impurity region in a depth direction is closer to the insulating surface than a maximum of an impurity concentration distribution in the second impurity region in a depth direction.Type: ApplicationFiled: May 22, 2014Publication date: September 11, 2014Applicant: Semiconductor Energy Laboratory Co., Ltd.Inventors: Junichi KOEZUKA, Satoshi SHINOHARA, Miki SUZUKI, Hideto OHNUMA
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Patent number: 8828844Abstract: A damaged region is formed by generation of plasma by excitation of a source gas, and by addition of ion species contained in the plasma from one of surfaces of a single crystal semiconductor substrate; an insulating layer is formed over the other surface of the single crystal semiconductor substrate; a supporting substrate is firmly attached to the single crystal semiconductor substrate so as to face the single crystal semiconductor substrate with the insulating layer interposed therebetween; separation is performed at the damaged region into the supporting substrate to which a single crystal semiconductor layer is attached and part of the single crystal semiconductor substrate by heating of the single crystal semiconductor substrate; dry etching is performed on a surface of the single crystal semiconductor layer attached to the supporting substrate; the single crystal semiconductor layer is recrystallized by irradiation of the single crystal semiconductor layer with a laser beam to melt at least part of theType: GrantFiled: October 8, 2008Date of Patent: September 9, 2014Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventors: Hideto Ohnuma, Tetsuya Kakehata, Akihisa Shimomura, Shinya Sasagawa, Motomu Kurata
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Patent number: 8823063Abstract: An SOI substrate having an SOI layer that can be used in practical applications even when a substrate with low upper temperature limit, such as a glass substrate, is used, is provided. A semiconductor device using such an SOI substrate, is provided. In bonding a single-crystal semiconductor layer to a substrate having an insulating surface or an insulating substrate, a silicon oxide film formed using organic silane as a material on one or both surfaces that are to form a bond is used. According to the present invention, a substrate with an upper temperature limit of 700° C. or lower, such as a glass substrate, can be used, and an SOI layer that is strongly bonded to the substrate can be obtained. In other words, a single-crystal semiconductor layer can be formed over a large-area substrate that is longer than one meter on each side.Type: GrantFiled: October 6, 2011Date of Patent: September 2, 2014Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventors: Hideto Ohnuma, Tetsuya Kakehata, Yoichi Iikubo
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Patent number: 8804060Abstract: It is an object of the present invention to provide a method for preventing a breaking and poor contact, without increasing the number of steps, thereby forming an integrated circuit with high driving performance and reliability. The present invention applies a photo mask or a reticle each of which is provided with a diffraction grating pattern or with an auxiliary pattern formed of a semi-translucent film having a light intensity reducing function to a photolithography step for forming wires in an overlapping portion of wires. And a conductive film to serve as a lower wire of a two-layer structure is formed, and then, a resist pattern is formed so that a first layer of the lower wire and a second layer narrower than the first layer are formed for relieving a steep step.Type: GrantFiled: September 14, 2009Date of Patent: August 12, 2014Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventors: Masayuki Sakakura, Hideto Ohnuma, Hideaki Kuwabara
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Patent number: 8766361Abstract: A semiconductor device is provided, which includes a single crystal semiconductor layer formed over an insulating surface and having a source region, a drain region, and a channel formation region, a gate insulating film covering the single crystal semiconductor layer and a gate electrode overlapping with the channel formation region with the gate insulating film interposed therebetween. In the semiconductor device, at least the drain region of the source and drain regions includes a first impurity region adjacent to the channel formation region and a second impurity region adjacent to the first impurity region. A maximum of an impurity concentration distribution in the first impurity region in a depth direction is closer to the insulating surface than a maximum of an impurity concentration distribution in the second impurity region in a depth direction.Type: GrantFiled: December 9, 2011Date of Patent: July 1, 2014Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventors: Junichi Koezuka, Satoshi Shinohara, Miki Suzuki, Hideto Ohnuma
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Publication number: 20140160385Abstract: This invention provides a semiconductor device having high operation performance and high reliability. An LDD region 707 overlapping with a gate wiring is arranged in an n-channel TFT 802 forming a driving circuit, and a TFT structure highly resistant to hot carrier injection is achieved. LDD regions 717, 718, 719 and 720 not overlapping with a gate wiring are arranged in an n-channel TFT 804 forming a pixel unit. As a result, a TFT structure having a small OFF current value is achieved. In this instance, an element belonging to the Group 15 of the Periodic Table exists in a higher concentration in the LDD region 707 than in the LDD regions 717, 718, 719 and 720.Type: ApplicationFiled: November 4, 2013Publication date: June 12, 2014Applicant: Semiconductor Energy Laboratory Co., Ltd.Inventors: Shunpei YAMAZAKI, Satoshi MURAKAMI, Jun KOYAMA, Yukio TANAKA, Hidehito KITAKADO, Hideto OHNUMA
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Publication number: 20140103409Abstract: An object is to provide an SOI substrate provided with a semiconductor layer which can be used practically even when a glass substrate is used as a base substrate. Another object is to provide a semiconductor device having high reliability using such an SOI substrate. An altered layer is formed on at least one surface of a glass substrate used as a base substrate of an SOI substrate to form the SOI substrate. The altered layer is formed on at least the one surface of the glass substrate by cleaning the glass substrate with solution including hydrochloric acid, sulfuric acid or nitric acid. The altered layer has a higher proportion of silicon oxide in its composition and a lower density than the glass substrate.Type: ApplicationFiled: December 19, 2013Publication date: April 17, 2014Applicant: Semiconductor Energy Laboratory Co., Ltd.Inventors: Tetsuya KAKEHATA, Hideto OHNUMA, Yoshiaki YAMAMOTO, Kenichiro MAKINO
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Publication number: 20140087543Abstract: It is an object of the present invention to provide a method for manufacturing an SOI substrate having an SOI layer that can be used in practical applications with high yield even when a flexible substrate such as a glass substrate or a plastic substrate is used. Further, it is another object of the present invention to provide a method for manufacturing a thin semiconductor device using such an SOI substrate with high yield. When a single-crystal semiconductor substrate is bonded to a flexible substrate having an insulating surface and the single-crystal semiconductor substrate is separated to manufacture an SOI substrate, one or both of bonding surfaces are activated, and then the flexible substrate having an insulating surface and the single-crystal semiconductor substrate are attached to each other.Type: ApplicationFiled: December 5, 2013Publication date: March 27, 2014Applicant: Semiconductor Energy Laboratory Co., Ltd.Inventors: Yasuhiro JINBO, Hironobu SHOJI, Hideto OHNUMA, Shunpei YAMAZAKI
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Patent number: 8658508Abstract: The present invention provides a method for manufacturing an SOI substrate, to improve planarity of a surface of a single crystal semiconductor layer after separation by favorably separating a single crystal semiconductor substrate even in the case where a non-mass-separation type ion irradiation method is used, and to improve planarity of a surface of a single crystal semiconductor layer after separation as well as to improve throughput.Type: GrantFiled: March 5, 2012Date of Patent: February 25, 2014Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventors: Takeshi Shichi, Junichi Koezuka, Hideto Ohnuma, Shunpei Yamazaki
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Patent number: 8633542Abstract: An object is to provide an SOI substrate provided with a semiconductor layer which can be used practically even when a glass substrate is used as a base substrate. Another object is to provide a semiconductor device having high reliability using such an SOI substrate. An altered layer is formed on at least one surface of a glass substrate used as a base substrate of an SOI substrate to form the SOI substrate. The altered layer is formed on at least the one surface of the glass substrate by cleaning the glass substrate with solution including hydrochloric acid, sulfuric acid or nitric acid. The altered layer has a higher proportion of silicon oxide in its composition and a lower density than the glass substrate.Type: GrantFiled: September 12, 2011Date of Patent: January 21, 2014Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventors: Tetsuya Kakehata, Hideto Ohnuma, Yoshiaki Yamamoto, Kenichiro Makino
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Patent number: 8629031Abstract: It is an object of the present invention to provide a method for manufacturing an SOI substrate having an SOI layer that can be used in practical applications with high yield even when a flexible substrate such as a glass substrate or a plastic substrate is used. Further, it is another object of the present invention to provide a method for manufacturing a thin semiconductor device using such an SOI substrate with high yield. When a single-crystal semiconductor substrate is bonded to a flexible substrate having an insulating surface and the single-crystal semiconductor substrate is separated to manufacture an SOI substrate, one or both of bonding surfaces are activated, and then the flexible substrate having an insulating surface and the single-crystal semiconductor substrate are attached to each other.Type: GrantFiled: February 5, 2013Date of Patent: January 14, 2014Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventors: Yasuhiro Jinbo, Hironobu Shoji, Hideto Ohnuma, Shunpei Yamazaki
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Patent number: 8629433Abstract: An object is to provide a method for manufacturing, with high yield, a semiconductor device having a crystalline semiconductor layer even if a substrate with low upper temperature limit. A groove is formed in a part of a semiconductor substrate to form a semiconductor substrate that has a projecting portion, and a bonding layer is formed to cover the projecting portion. In addition, before the bonding layer is formed, a portion of the semiconductor substrate to be the projecting portion is irradiated with accelerated ions to form a brittle layer. After the bonding layer and the supporting substrate are bonded together, heat treatment for separation of the semiconductor substrate is performed to provide a semiconductor layer over the supporting substrate. The semiconductor layer is selectively etched, and a semiconductor element is formed and a semiconductor device is manufactured.Type: GrantFiled: January 25, 2011Date of Patent: January 14, 2014Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventors: Shunpei Yamazaki, Hideto Ohnuma
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Patent number: 8629030Abstract: The present invention provides a method for manufacturing an SOI substrate, to improve planarity of a surface of a single crystal semiconductor layer after separation by favorably separating a single crystal semiconductor substrate even in the case where a non-mass-separation type ion irradiation method is used, and to improve planarity of a surface of a single crystal semiconductor layer after separation as well as to improve throughput.Type: GrantFiled: March 5, 2012Date of Patent: January 14, 2014Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventors: Takeshi Shichi, Junichi Koezuka, Hideto Ohnuma, Shunpei Yamazaki
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Patent number: 8598013Abstract: To provide a method for manufacturing an SOI substrate provided with a semiconductor layer which can be used practically even when a substrate having a low heat-resistant temperature, such as a glass substrate or the like is used. The semiconductor layer is transferred to a supporting substrate by the steps of irradiating a semiconductor wafer with ions from one surface to form a damaged layer; forming an insulating layer over one surface of the semiconductor wafer; attaching one surface of the supporting substrate to the insulating layer formed over the semiconductor wafer and performing heat treatment to bond the supporting substrate to the semiconductor wafer; and performing separation at the damaged layer into the semiconductor wafer and the supporting substrate. The damaged layer remaining partially over the semiconductor layer is removed by wet etching and a surface of the semiconductor layer is irradiated with a laser beam.Type: GrantFiled: October 8, 2008Date of Patent: December 3, 2013Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventors: Shunpei Yamazaki, Hideto Ohnuma, Yoichi Iikubo, Yoshiaki Yamamoto, Kenichiro Makino
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Patent number: 8592907Abstract: It is an object to achieve high performance of a semiconductor integrated circuit depending on not only a microfabrication technique but also another way and to achieve low power consumption of a semiconductor integrated circuit. A semiconductor device is provided in which a crystal orientation or a crystal axis of a single-crystalline semiconductor layer for a MISFET having a first conductivity type is different from that of a single-crystalline semiconductor layer for a MISFET having a second conductivity type. A crystal orientation or a crystal axis is such that mobility of carriers traveling in a channel length direction is increased in each MISFET. With such a structure, mobility of carriers flowing in a channel of a MISFET is increased, and a semiconductor integrated circuit can be operated at higher speed. Further, low voltage driving becomes possible, and low power consumption can be achieved.Type: GrantFiled: March 30, 2011Date of Patent: November 26, 2013Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventor: Hideto Ohnuma
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Patent number: 8574976Abstract: A TFT having a high threshold voltage is connected to the source electrode of each TFT that constitutes a CMOS circuit. In another aspect, pixel thin-film transistors are constructed such that a thin-film transistor more distant from a gate line drive circuit has a lower threshold voltage. In a further aspect, a control film that is removable in a later step is formed on the surface of the channel forming region of a TFT, and doping is performed from above the control film.Type: GrantFiled: October 14, 2010Date of Patent: November 5, 2013Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventors: Shunpei Yamazaki, Naoto Kusumoto, Hideto Ohnuma, Koichiro Tanaka
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Patent number: 8575619Abstract: This invention provides a semiconductor device having high operation performance and high reliability. An LDD region 707 overlapping with a gate wiring is arranged in an n-channel TFT 802 forming a driving circuit, and a TFT structure highly resistant to hot carrier injection is achieved. LDD regions 717, 718, 719 and 720 not overlapping with a gate wiring are arranged in an n-channel TFT 804 forming a pixel unit. As a result, a TFT structure having a small OFF current value is achieved. In this instance, an element belonging to the Group 15 of the Periodic Table exists in a higher concentration in the LDD region 707 than in the LDD regions 717, 718, 719 and 720.Type: GrantFiled: September 11, 2012Date of Patent: November 5, 2013Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventors: Shunpei Yamazaki, Satoshi Murakami, Jun Koyama, Yukio Tanaka, Hidehito Kitakado, Hideto Ohnuma