Patents by Inventor Hidetoshi Ishida
Hidetoshi Ishida has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20190239398Abstract: It is an object of the present invention to provide a technique with which it is possible to improve the production yield of a shield member that includes a drain wire with a free end portion by cutting a long drain wire-attached shield member to a desired length. The shield member includes a shield portion and a drain wire. The shield portion can shield an electric wire. The drain wire includes: a holding portion provided between a first end and a second end of the shield portion and held in the shield portion; and an extension portion that is continuous with the holding portion and extends outward from the shield portion. At least a portion of the holding portion extends between the first end and the second end of the shield portion while having excess length.Type: ApplicationFiled: July 10, 2017Publication date: August 1, 2019Applicants: AutoNetworks Technologies, Ltd., Sumitomo Wiring Systems, Ltd., Sumitomo Electric Industries, Ltd.Inventors: Housei MIZUNO, Hidetoshi ISHIDA, Yasuyuki YAMAMOTO
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Publication number: 20190207381Abstract: The present invention reliably prevents a problem caused by a short circuit. A short circuit protection device for a battery monitoring system according to the present invention includes: a battery that is an assembled battery including a plurality of battery cells; a battery monitoring apparatus for detecting the voltage of the battery; and a plurality of electric wires that connect the battery and the battery monitoring apparatus, and in each of which an eluting portion is formed midway in a lengthwise direction, the eluting portion being a portion where an insulating coating has been stripped and a core wire is exposed. When the eluting portions are immersed in an electrolyte, the eluting portions elute into the electrolyte, thereby melt and are cut off.Type: ApplicationFiled: June 8, 2017Publication date: July 4, 2019Applicants: AUTONETWORKS TECHNOLOGIES, LTD., SUMITOMO WIRING SYSTEMS, LTD., SUMITOMO ELECTRIC INDUSTRIES, LTD.Inventors: Hidetoshi ISHIDA, Shinichi TAKASE
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Patent number: 10297993Abstract: A protective member-attached wire is provided with: an electric wire; and a protective member that is made of a sheet-shaped nonwoven member and is wrapped around the electric wire to cover the electric wire. The protective member includes: a first portion obtained by heating a portion of the nonwoven member; and a second portion that is softer than the first portion of the nonwoven member. The first portion and the second portion are each distributed over the entire circumference of the electric wire in a circumferential direction of the electric wire, and are distributed over the entire protective member in a longitudinal direction of the electric wire.Type: GrantFiled: November 10, 2016Date of Patent: May 21, 2019Assignees: AUTONETWORKS TECHNOLOGIES, LTD., SUMITOMO WIRING SYSTEMS, LTD., SUMITOMO ELECTRIC INDUSTRIES, LTD.Inventors: Hidetoshi Ishida, Housei Mizuno, Yasuyuki Yamamoto, Atsushi Murata
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Patent number: 10256558Abstract: A movable member (30) provided in a housing (10) is formed with a cover (32) configured to cover inserting edges (45) on a tip of a circuit board (41) in an inserting direction into a board accommodation space (15) when the circuit board (41) is inserted into the board accommodation space (15) and a receiving surface (34) configured to move the movable member (30) integrally with the circuit board (41) to a back side of the board accommodation space (15) by being pushed by the circuit board (41). The movable member (30) and the circuit board (41) are formed with locks (38, 46) configured to move the movable member (30) integrally with the circuit board (41) in a withdrawing direction from the board accommodation space (15) by locking each other.Type: GrantFiled: August 17, 2016Date of Patent: April 9, 2019Assignees: AutoNetworks Technologies, Ltd., Sumitomo Wiring Systems, Ltd, Sumitomo Electric Industries, Ltd.Inventors: Masanori Moriyasu, Masaaki Tabata, Hidetoshi Ishida, Hajime Matsui
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Publication number: 20190027849Abstract: A movable member (30) provided in a housing (10) is formed with a cover (32) configured to cover inserting edges (45) on a tip of a circuit board (41) in an inserting direction into a board accommodation space (15) when the circuit board (41) is inserted into the board accommodation space (15) and a receiving surface (34) configured to move the movable member (30) integrally with the circuit board (41) to a back side of the board accommodation space (15) by being pushed by the circuit board (41). The movable member (30) and the circuit board (41) are formed with locks (38, 46) configured to move the movable member (30) integrally with the circuit board (41) in a withdrawing direction from the board accommodation space (15) by locking each other.Type: ApplicationFiled: August 17, 2016Publication date: January 24, 2019Inventors: Masanori Moriyasu, Masaaki Tabata, Hidetoshi Ishida, Hajime Matsui
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Publication number: 20180331521Abstract: A protective member-attached wire is provided with: an electric wire; and a protective member that is made of a sheet-shaped nonwoven member and is wrapped around the electric wire to cover the electric wire. The protective member includes: a first portion obtained by heating a portion of the nonwoven member; and a second portion that is softer than the first portion of the nonwoven member. The first portion and the second portion are each distributed over the entire circumference of the electric wire in a circumferential direction of the electric wire, and are distributed over the entire protective member in a longitudinal direction of the electric wire.Type: ApplicationFiled: November 10, 2016Publication date: November 15, 2018Applicants: AUTONETWORKS TECHNOLOGIES, LTD., SUMITOMO WIRING SYSTEMS, LTD., SUMITOMO ELECTRIC INDUSTRIES, LTD.Inventors: Hidetoshi ISHIDA, Housei MIZUNO, Yasuyuki YAMAMOTO, Atsushi MURATA
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Patent number: 10096919Abstract: It is aimed to avoid the abrasion of a contact portion of a terminal fitting. When a harness-side housing (4) is connected to a board-side housing (1), a contact portion (12) of a terminal fitting (3) resiliently contacts a circuit board (2), whereas a body portion (5) of the terminal fitting (3) is pressed against a ceiling wall (19) of a cavity (14). The body portion (5) is formed with a projecting edge (13). When there is a thermal expansion difference in an arrangement direction of the cavities (14) between the circuit board (2) and the harness-side housing (4), the terminal fitting (3) pivots with a resilient abutting part of the contact portion (12) and the circuit board (2) serving as a supporting point.Type: GrantFiled: March 10, 2016Date of Patent: October 9, 2018Assignees: AUTONETWORKS TECHNOLOGIES, LTD., SUMITOMO WIRING SYSTEMS, LTD., SUMITOMO ELECTRIC INDUSTRIES, LTD.Inventors: Hidetoshi Ishida, Masanori Moriyasu
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Patent number: 9941437Abstract: A solar cell has a condenser lens and a solar cell element, the solar cell element including an n-type InGaAs layer, an n-type GaAs layer, an n-type InGaP layer, the first InGaAs peripheral part having a thickness (d2), and a width (w2), the second InGaAs peripheral part having a thickness (d3), and a width (w3), the first GaAs peripheral part having a thickness (d5), and a width (w4), the second GaAs peripheral part a thickness (d6), and a width (w5), the first InGaP peripheral part having a thickness (d8), and a width (w6), the second InGaP peripheral part having a thickness (d9), and a width (w7), the following inequation set being satisfied: 1 nm?(d2, d3, d5, and d6)?4 nm, 1 nm?(d8 and d9)?5 nm, 100 nm?(w2, w3, w4, w5, w6, and w7), the InGaAs center part having a thickness (w1), a window layer has a range S irradiated by sunlight having a width (w8); w8?w1.Type: GrantFiled: December 11, 2013Date of Patent: April 10, 2018Assignee: PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO., LTD.Inventors: Akio Matsushita, Akihiro Itoh, Tohru Nakagawa, Hidetoshi Ishida
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Publication number: 20180097303Abstract: It is aimed to avoid the abrasion of a contact portion of a terminal fitting. When a harness-side housing (4) is connected to a board-side housing (1), a contact portion (12) of a terminal fitting (3) resiliently contacts a circuit board (2), whereas a body portion (5) of the terminal fitting (3) is pressed against a ceiling wall (19) of a cavity (14). The body portion (5) is formed with a projecting edge (13). When there is a thermal expansion difference in an arrangement direction of the cavities (14) between the circuit board (2) and the harness-side housing (4), the terminal fitting (3) pivots with a resilient abutting part of the contact portion (12) and the circuit board (2) serving as a supporting point.Type: ApplicationFiled: March 10, 2016Publication date: April 5, 2018Inventors: Hidetoshi Ishida, Masanori Moriyasu
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Patent number: 9116307Abstract: A sleeve for an optical connector into which a ferrule arranged to hold an optical fiber is to be inserted, and by which an optical connector in which the sleeve is to be housed can be reduced in size in a direction that the optical connector is fitted into a counterpart optical connector. A sleeve for an optical connector includes a portion having a tube shape, into which a ferrule is to be inserted, and a hook portion at one end of the sleeve, the hook portion protruding in a diameter direction of the tube-shaped portion.Type: GrantFiled: October 3, 2011Date of Patent: August 25, 2015Assignees: AUTONETWORKS TECHNOLOGIES, LTD., SUMITOMO WIRING SYSTEMS, LTD., SUMITOMO ELECTRIC INDUSTRIES, LTD.Inventors: Hiroyoshi Maesoba, Tetsuji Tanaka, Hidetoshi Ishida
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Patent number: 8905650Abstract: A fiber-optic cable with a fitting capable of increasing connection strength between a fiber-optic cable and an optical connector, which includes a fiber-optic cable including a sheath and a tensile member, an inner ring mounted on a circumference of the sheath from a position where the tensile member is drawn out of the sheath through a slit to a front end of the sheath, and a fitting mounted on the circumference and including a first portion mounted from the position where the tensile member is drawn out of the sheath to a position of the sheath on a side opposite to the ring side, and a second portion mounted while covering a circumference of the ring, wherein the first portion connects with the sheath, and the end portion of the tensile member is sandwiched by the ring and the second portion.Type: GrantFiled: September 5, 2011Date of Patent: December 9, 2014Assignees: Autonetworks Technologies, Ltd., Sumitomo Wiring Systems, Ltd., Sumitomo Electric Industries, Ltd.Inventors: Hidetoshi Ishida, Hiroyoshi Maesoba, Tetsuji Tanaka
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Patent number: 8884333Abstract: A nitride semiconductor device includes a semiconductor multilayer formed on a substrate, a first ohmic electrode and a Schottky electrode spaced apart from each other on the semiconductor multilayer; and a passivation film covering a top of the semiconductor multilayer. The semiconductor multilayer 102 includes a first nitride semiconductor layer, a second nitride semiconductor layer, and a p-type third nitride semiconductor layer 124 sequentially formed on the substrate. The third nitride semiconductor layer contains p-type impurities, and is selectively formed between the first ohmic electrode and the Schottky electrode in contact with the Schottky electrode.Type: GrantFiled: April 29, 2014Date of Patent: November 11, 2014Assignee: Panasonic CorporationInventors: Daisuke Shibata, Masahiro Hikita, Hidetoshi Ishida, Tetsuzo Ueda
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Publication number: 20140231873Abstract: A nitride semiconductor device includes a semiconductor multilayer formed on a substrate, a first ohmic electrode and a Schottky electrode spaced apart from each other on the semicnductor multilayer; and a passivation film covering a top of the semiconductor multilayer. The semiconductor multilayer 102 includes a first nitride semiconductor layer, a second nitride semiconductor layer, and a p-type third nitride semiconductor layer 124 sequentially formed on the substrate. The third nitride semiconductor layer contains p-type impurities, and is selectively formed between the first ohmic electrode and the Schottky electrode in contact with the Schottky electrode.Type: ApplicationFiled: April 29, 2014Publication date: August 21, 2014Applicant: PANASONIC CORPORATIONInventors: Daisuke SHIBATA, Masahiro HIKITA, Hidetoshi ISHIDA, Tetsuzo UEDA
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Patent number: 8748995Abstract: A nitride semiconductor device includes a nitride semiconductor multilayer including an active region, and first and second electrodes, each having a finger-like structure and formed on the active region to be spaced from each other. A first electrode interconnect is formed on the first electrode. A second electrode interconnect is formed on the second electrode. A second insulating film is formed to cover the first and second electrode interconnects. A first metal layer is formed on the second insulating film. The first metal layer is formed above the active region with the second insulating film interposed therebetween, and is coupled to the first electrode interconnect.Type: GrantFiled: January 3, 2013Date of Patent: June 10, 2014Assignee: Panasonic CorporationInventors: Kazuhiro Kaibara, Hidetoshi Ishida, Tetsuzo Ueda
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Patent number: 8748941Abstract: A nitride semiconductor device includes a semiconductor multilayer formed on a substrate, a first ohmic electrode and a Schottky electrode spaced apart from each other on the semiconductor multilayer; and a passivation film covering a top of the semiconductor multilayer. The semiconductor multilayer 102 includes a first nitride semiconductor layer, a second nitride semiconductor layer, and a p-type third nitride semiconductor layer 124 sequentially formed on the substrate. The third nitride semiconductor layer contains p-type impurities, and is selectively formed between the first ohmic electrode and the Schottky electrode in contact with the Schottky electrode.Type: GrantFiled: February 13, 2012Date of Patent: June 10, 2014Assignee: Panasonic CorporationInventors: Daisuke Shibata, Masahiro Hikita, Hidetoshi Ishida, Tetsuzo Ueda
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Publication number: 20140096818Abstract: A solar cell has a condenser lens and a solar cell element, the solar cell element including an n-type InGaAs layer, an n-type GaAs layer, an n-type InGaP layer, the first InGaAs peripheral part having a thickness (d2), and a width (w2), the second InGaAs peripheral part having a thickness (d3), and a width (w3), the first GaAs peripheral part having a thickness (d5), and a width (w4), the second GaAs peripheral part a thickness (d6), and a width (w5), the first InGaP peripheral part having a thickness (d8), and a width (w6), the second InGaP peripheral part having a thickness (d9), and a width (w7), the following inequation set being satisfied: 1 nm?(d2, d3, d5, and d6)?4 nm, 1 nm?(d8 and d9)?5 nm, 100 nm?(w2, w3, w4, w5, w6, and w7), the InGaAs center part having a thickness (w1), a window layer has a range S irradiated by sunlight having a width (w8); w8?w1.Type: ApplicationFiled: December 11, 2013Publication date: April 10, 2014Applicant: Panasonic CorporationInventors: Akio MATSUSHITA, Akihiro ITOH, Tohru NAKAGAWA, Hidetoshi ISHIDA
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Patent number: 8604338Abstract: A method for generating electric power with use of a solar cell includes steps of: (a) preparing the solar cell including a condensing lens and a solar cell element, wherein the following inequation set (I) is satisfied: d2<d1, d3<d1, 1 nanometer?d2?4 nanometers, 1 nanometer?d3?4 nanometers, 100 nanometers?w2, and 100 nanometers?w3 . . . (I); and (b) irradiating a region S which is included in the surface of the p-type window layer through the condensing lens with light in such a manner that the following inequation (II) is satisfied so as to generate a potential difference between the n-side electrode (110) and the p-side electrode (109): w4?w1 . . . (II).Type: GrantFiled: May 11, 2012Date of Patent: December 10, 2013Assignee: Panasonic CorporationInventors: Akio Matsushita, Akihiro Itoh, Tohru Nakagawa, Hidetoshi Ishida
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Publication number: 20130183002Abstract: A sleeve for an optical connector into which a ferrule arranged to hold an optical fiber is to be inserted, and by which an optical connector in which the sleeve is to be housed can be reduced in size in a direction that the optical connector is fitted into a counterpart optical connector. A sleeve for an optical connector includes a portion having a tube shape, into which a ferrule is to be inserted, and a hook portion at one end of the sleeve, the hook portion protruding in a diameter direction of the tube-shaped portion.Type: ApplicationFiled: October 3, 2011Publication date: July 18, 2013Applicants: AUTONETWORKS TECHNOLOGIES, LTD., SUMITOMO ELECTRIC INDUSTRIES, LTD., SUMITOMO WIRING SYSTEMS, LTD.Inventors: Hiroyoshi Maesoba, Tetsuji Tanaka, Hidetoshi Ishida
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Patent number: 8441035Abstract: The present invention has an object to provide an FET and a method of manufacturing the FET that are capable of increasing the threshold voltage as well as decreasing the on-resistance. The FET of the present invention includes a first undoped GaN layer; a first undoped AlGaN layer formed on the first undoped GaN layer, having a band gap energy greater than that of the first undoped GaN layer; a second undoped GaN layer formed on the first undoped AlGaN layer; a second undoped AlGaN layer formed on the second undoped GaN layer, having a band gap energy greater than that of the second undoped GaN layer; a p-type GaN layer formed in the recess of the second undoped AlGaN layer; a gate electrode formed on the p-type GaN layer; and a source electrode and a drain electrode which are formed in both lateral regions of the gate electrode, wherein a channel is formed at the heterojunction interface between the first undoped GaN layer and the first undoped AlGaN layer.Type: GrantFiled: June 1, 2011Date of Patent: May 14, 2013Assignee: Panasonic CorporationInventors: Masahiro Hikita, Hidetoshi Ishida, Tetsuzo Ueda
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Patent number: RE45989Abstract: A semiconductor device includes a semiconductor layer stack 13 formed on a substrate 11 and having a channel region, a first electrode 16A and a second electrode 16B formed spaced apart from each other on the semiconductor layer stack 13, a first gate electrode 18A formed between the first electrode 16A and the second electrode 16B, and a second gate electrode 18B formed between the first gate electrode 18A and the second electrode 16B. A first control layer 19A having a p-type conductivity is formed between the semiconductor layer stack 13 and the first gate electrode 18A.Type: GrantFiled: June 10, 2014Date of Patent: April 26, 2016Assignee: PANASONIC CORPORATIONInventors: Tatsuo Morita, Manabu Yanagihara, Hidetoshi Ishida, Yasuhiro Uemoto, Hiroaki Ueno, Tsuyoshi Tanaka, Daisuke Ueda