Abstract: A fiber-optic cable with a fitting capable of increasing connection strength between a fiber-optic cable and an optical connector, which includes a fiber-optic cable including a sheath and a tensile member, an inner ring mounted on a circumference of the sheath from a position where the tensile member is drawn out of the sheath through a slit to a front end of the sheath, and a fitting mounted on the circumference and including a first portion mounted from the position where the tensile member is drawn out of the sheath to a position of the sheath on a side opposite to the ring side, and a second portion mounted while covering a circumference of the ring, wherein the first portion connects with the sheath, and the end portion of the tensile member is sandwiched by the ring and the second portion.

Abstract: A method for generating electric power including the steps of: (a) preparing a solar cell having a condensing lens and a solar cell element, wherein the solar cell element includes an n-type GaAs layer, a p-type GaAs layer, a quantum tunneling layer, an n-type InGaP layer, a p-type InGaP layer, a p-type window layer, an n-side electrode, and a p-side electrode, and satisfies the following equation (I): d2<d1, d3<d1, nanometer?d2?4 nanometers, 1 nanometer?d3?4 nanometers, d5<d4, d6<d4, 1 nanometer?d5?5 nanometers, 1 nanometer?d6?5 nanometers, 100 nanometers?w2, 100 nanometers?w3, 100 nanometers?w4, and 100 nanometers?w5. . . (I); and (b) irradiating a region S which is included in the surface of the p-type window layer through the condensing lens with light to satisfy the following equation (II) in order to generate a potential difference between the n-side electrode and the p-side electrode: w6?w1. . . (II).

Abstract: A method for generating electric power including the steps of: (a) preparing a solar cell having a condensing lens and a solar cell element, wherein the solar cell element includes an n-type GaAs layer, a p-type GaAs layer, a quantum tunneling layer, an n-type InGaP layer, a p-type InGaP layer, a p-type window layer, an n-side electrode, and a p-side electrode, and satisfies the following equation (I): d2<d1, d3<d1, 1 nanometer?d2?4 nanometers, 1 nanometer?d3?4 nanometers, d5<d4, d6<d4, 1 nanometer?d5?5 nanometers, 1 nanometer?d6?5 nanometers, 100 nanometers?w2, 100 nanometers?w3, 100 nanometers?w4, and 100 nanometers?w5 . . . (I); and (b) irradiating a region S which is included in the surface of the p-type window layer through the condensing lens with light to satisfy the following equation (II) in order to generate a potential difference between the n-side electrode and the p-side electrode: w6?w1 . . . (II).

Abstract: The purpose of the present invention is to provide a solar cell with higher conversion efficiency. The method comprises steps of: (a) preparing the solar cell comprising a condensing lens (101) and a solar cell element (102), wherein the following inequation set (I) is satisfied: d2<d1,d3<d1,1 nanometer?d2?4 nanometers,1 nanometer?d3?4 nanometers,100 nanometers?w2,and 100 nanometers?w3??(I); and (b) irradiating a region S which is included in the surface of the p-type window layer (105) through the condensing lens (101) with light in such a manner that the following inequation (II) is satisfied so as to generate a potential difference between the n-side electrode (110) and the p-side electrode (109): w4?w1??(II).

Abstract: A semiconductor device includes a semiconductor layer stack 13 formed on a substrate 11 and having a channel region, a first electrode 16A and a second electrode 16B formed spaced apart from each other on the semiconductor layer stack 13, a first gate electrode 18A formed between the first electrode 16A and the second electrode 16B, and a second gate electrode 18B formed between the first gate electrode 18A and the second electrode 16B. A first control layer 19A having a p-type conductivity is formed between the semiconductor layer stack 13 and the first gate electrode 18A.

Abstract: A nitride semiconductor device includes a semiconductor multilayer formed on a substrate, a first ohmic electrode and a Schottky electrode spaced apart from each other on the semiconductor multilayer; and a passivation film covering a top of the semiconductor multilayer. The semiconductor multilayer 102 includes a first nitride semiconductor layer, a second nitride semiconductor layer, and a p-type third nitride semiconductor layer 124 sequentially formed on the substrate. The third nitride semiconductor layer contains p-type impurities, and is selectively formed between the first ohmic electrode and the Schottky electrode in contact with the Schottky electrode.

Abstract: A normally-off type field effect transistor includes: a first semiconductor layer which is made of a first hexagonal crystal with 6 mm symmetry and has a main surface including a C-axis of the first hexagonal crystal; a second semiconductor layer which is formed on the main surface of the first semiconductor layer and is made of a second hexagonal crystal with 6 mm symmetry having a band gap different from a band gap of the first hexagonal crystal; and a gate electrode, a source electrode and a drain electrode that are formed on the second semiconductor layer. Here, the film thickness of the first nitride semiconductor layer is 1.5 ?m or less and the second semiconductor layer is doped with impurities at a dose of 1×1013 cm?2 or more.

Abstract: The present invention has as an object to provide a FET having low on-resistance. The FET according to the present invention includes: first nitride semiconductor layer; a second nitride semiconductor layer formed on the first nitride semiconductor layer and having a higher band gap energy than the first nitride semiconductor layer; a third nitride semiconductor layer formed on the second nitride semiconductor layer; a fourth nitride semiconductor layer formed on the third nitride semiconductor layer and having a higher band gap energy than the third nitride semiconductor layer. A channel is formed in a heterojunction interface between the first nitride semiconductor layer and the second nitride semiconductor layer.

Abstract: The present invention has an object to provide an FET and a method of manufacturing the FET that are capable of increasing the threshold voltage as well as decreasing the on-resistance. The FET of the present invention includes a first undoped GaN layer; a first undoped AlGaN layer formed on the first undoped GaN layer, having a band gap energy greater than that of the first undoped GaN layer; a second undoped GaN layer formed on the first undoped AlGaN layer; a second undoped AlGaN layer formed on the second undoped GaN layer, having a band gap energy greater than that of the second undoped GaN layer; a p-type GaN layer formed in the recess of the second undoped AlGaN layer; a gate electrode formed on the p-type GaN layer; and a source electrode and a drain electrode which are formed in both lateral regions of the gate electrode, wherein a channel is formed at the heterojunction interface between the first undoped GaN layer and the first undoped AlGaN layer.

Abstract: A high breakdown voltage GaN-based transistor is provided on a silicon substrate. A nitride semiconductor device including: a silicon substrate, a SiO2 layer stacked on the silicon substrate and having a film thickness 100 nm or more; a silicon layer stacked on the SiO2 layer; a buffer layer stacked on the silicon layer; a GaN layer stacked on the buffer layer; an AlGaN layer stacked on the GaN layer; and a source electrode, a drain electrode, and a gate electrode that are formed on the AlGaN layer, and edge sidewalls of the silicon layer, the buffer layer, the GaN layer, and the AlGaN layer contact an increased-resistivity region.

Abstract: A semiconductor device includes: a semiconductor layer; at least one electrode formed on a semiconductor layer to be in contact with the semiconductor layer; and a passivation film covering the semiconductor layer and at least part of the top surface of the electrode to protect the semiconductor layer and formed of a plurality of sub-films. The passivation film includes a first sub-film made of aluminum nitride.

Abstract: A plasma display panel driving device includes an electrode driving unit for generating a drive pulse to be applied to an electrode of a plasma display panel. The electrode driving unit has a plurality of switches. At least one of the plurality of switches is a switch device including a dual-gate semiconductor device. The dual-gate semiconductor device 10 has a semiconductor multilayer 13 formed on a substrate 11 and made of a nitride semiconductor or a silicon carbide semiconductor, a source electrode 16 and a drain electrode 17 formed and spaced apart from each other on the semiconductor multilayer 13, and a first gate electrode 18A and a second gate electrode 18B formed between the source electrode 16 and the drain electrode 17, successively from the source electrode 16 side.

Abstract: A field effect transistor includes a first semiconductor layer made of a multilayer of a plurality of semiconductor films and a second semiconductor layer formed on the first semiconductor layer. A source electrode and a drain electrode are formed on the second semiconductor layer to be spaced from each other. An opening having an insulating film on its inner wall is formed in a portion of the second semiconductor layer sandwiched between the source electrode and the drain electrode so as to expose the first semiconductor layer therein. A gate electrode is formed in the opening to be in contact with the insulating film and the first semiconductor layer on the bottom of the opening.

Abstract: To provide a semiconductor device that has a sufficiently low on-resistance and excellent low-capacitance and high-speed characteristics as compared with conventional GaN-based diodes. The semiconductor device includes: a substrate (101); a buffer layer (102); a stack structure (103 and 104) including at least one heterojunction unit (103 and 104) that is a stack of a layer (GaN layer 103) made of a nitride semiconductor and a layer (AlGaN layer 104) made of another nitride semiconductor having a larger band gap than the nitride semiconductor (GaN layer 103); a Schottky electrode (106) that is placed at a first end of the stack structure (103 and 104) and forms a Schottky barrier contact with the heterojunction unit (103 and 104); and an ohmic electrode (107) that is placed at a second end of the stack structure (103 and 104) and forms an ohmic contact with the heterojunction unit (103 and 104).

Abstract: A semiconductor device includes a semiconductor layer stack 13 formed on a substrate 11 and having a channel region, a first electrode 16A and a second electrode 16B formed spaced apart from each other on the semiconductor layer stack 13, a first gate electrode 18A formed between the first electrode 16A and the second electrode 16B, and a second gate electrode 18B formed between the first gate electrode 18A and the second electrode 16B. A first control layer 19A having a p-type conductivity is formed between the semiconductor layer stack 13 and the first gate electrode 18A.

Abstract: A semiconductor device includes: a semiconductor layer; at least one electrode formed on a semiconductor layer to be in contact with the semiconductor layer; and a passivation film covering the semiconductor layer and at least part of the top surface of the electrode to protect the semiconductor layer and formed of a plurality of sub-films. The passivation film includes a first sub-film made of aluminum nitride.

Abstract: There is provided a normally-off type transistor made of a nitride semiconductor. The transistor includes; an undoped GaN layer which forms a channel region; an undoped Al0.2Ga0.8N layer which is formed on the undoped GaN layer and has a band gap larger than that of the undoped GaN layer; a p-type Al0.2Ga0.8N control layer which is formed on the undoped Al0.2Ga0.8N layer, has a p-type conductivity and forms a control region; an Ni gate electrode which contacts with the p-type Al0.2Ga0.8N control layer; a Ti/Al source electrode and a Ti/Al drain electrode which are formed beside the p-type Al0.2Ga0.8N control layer; and an Ni ohmic electrode which is connected to the undoped GaN layer and serves as a hole absorbing electrode. With this transistor, it is possible to achieve a large-current operation and a high switching speed.

Abstract: A semiconductor device includes: a semiconductor layer; at least one electrode formed on a semiconductor layer to be in contact with the semiconductor layer; and a passivation film covering the semiconductor layer and at least part of the top surface of the electrode to protect the semiconductor layer and formed of a plurality of sub-films. The passivation film includes a first sub-film made of aluminum nitride.

Abstract: A bidirectional switch includes a field-effect transistor having a first ohmic electrode, a second ohmic electrode and a gate electrode, and a control circuit for controlling between a conduction state and a cut-off state by applying a bias voltage to the gate electrode. The control circuit applies the bias voltage from the first ohmic electrode as a reference when a potential of the second ohmic electrode is higher than the potential of the first ohmic electrode, and applies the bias voltage from the second ohmic electrode as a reference when the potential of the second electrode is lower than the potential of the first ohmic electrode.

Abstract: An object of the present invention is to provide a semiconductor device and a manufacturing method thereof which can realize a normally-off field-effect transistor made of a III group nitride semiconductor. The present invention includes: placing a sapphire substrate in a crystal growth chamber; forming a low-temperature GaN buffer layer made of GaN as the III group nitride semiconductor, on a main surface of the sapphire substrate by a MOCVD method; and forming a GaN layer on the low-temperature GaN buffer layer by the MOCVD method. Here, a [11-20] axis of the GaN layer is perpendicular to the main surface of the sapphire substrate.