Abstract: Provided is a base station that performs feedback with regard to data transmission. The base station includes a downlink feedback information (DFI) generation unit and a transmitter. On the basis of a resource allocation configuration that was configured by a terminal, the DFI generation unit determines a transmission method for feedback information that includes a response signal regarding uplink data. The transmitter transmits the feedback information on the basis of the transmission method.

Abstract: A base station (100, 300) is provided with a transmitter and a receiver. The transmitter (109) transmits a downlink signal in a downlink transmission region, in a time unit that includes the downlink transmission region, an uplink transmission region, and a gap period that is a switching point between the downlink transmission region and the uplink transmission region. The receiver (111) receives an uplink signal in the uplink transmission region, in the time unit. Furthermore, a delay tolerant signal for which a delay is tolerated more than for the downlink signal and the uplink signal is mapped to within the gap period.

Abstract: Disclosed is a semiconductor memory device having a data retention operating mode. When an entry into the data retention operating mode is performed, parity information on data of the memory cells is calculated and the error correction on the memory cells is carried out at a time of an exit from the data retention operating mode, by an ECC (Error Correction Circuit). The semiconductor memory device includes means for outputting from an NC pin flag information indicating that the semiconductor memory device is the one including the data retention operating mode, that the exit processing from the data retention operating mode is under way, and that the error correction cannot be performed.

Abstract: When a DRAM enters an operation mode in which only a data storing operation is performed, a check bit for error detection and correction for plural data is generated and stored. Refresh operation is performed in a refresh cycle which is made long within an allowable range of an error occurrence by an error correcting operation using the check bit. Before the DRAM returns to the normal operation mode from the data holding operation mode, an error bit is corrected by using the data and the check bit.

Abstract: When a DRAM enters an operation mode in which only a data storing operation is performed, a check bit for error detection and correction for plural data is generated and stored. Refresh operation is performed in a refresh cycle which is made long within an allowable range of an error occurrence by an error correcting operation using the check bit. Before the DRAM returns to the normal operation mode from the data holding operation mode, an error bit is corrected by using the data and the check bit.

Abstract: When a DRAM enters an operation mode in which only a data storing operation is performed, a check bit for error detection and correction for plural data is generated and stored. Refresh operation is performed in a refresh cycle which is made long within an allowable range of an error occurrence by an error correcting operation using the check bit. Before the DRAM returns to the normal operation mode from the data holding operation mode, an error bit is corrected by using the data and the check bit.

Abstract: Disclosed is a semiconductor memory device having a data retention operating mode. When an entry into the data retention operating mode is performed, parity information on data of the memory cells is calculated and the error correction on the memory cells is carried out at a time of an exit from the data retention operating mode, by an ECC (Error Correction Circuit). The semiconductor memory device includes means for outputting from an NC pin flag information indicating that the semiconductor memory device is the one including the data retention operating mode, that the exit processing from the data retention operating mode is under way, and that the error correction cannot be performed.

Abstract: A semiconductor IC device includes, in a substrate, a P-type well region having a dynamic memory array section and applied with a reduced back bias voltage suitable for refreshing. Also included is a P-well region where N-channel MOSFETs of a peripheral circuit are formed. This P-well region is applied with a back bias voltage of an absolute value smaller than that applied to the P-type well of the memory array section. A P-type well section, where there are formed N-channel MOSFETs of an input circuit or an output circuit connected with external terminals, is applied with a back bias voltage of an absolute value large enough to provide a measure of protection against undershoot, while the refresh characteristics are improved by reducing the leakage current between the source/drain region connected with a capacitor and the P-type well, to thereby raise the operation speed of the peripheral circuit.

Abstract: A semiconductor IC device includes, in a substrate, a P-type well region having a dynamic memory array section and applied with a reduced back bias voltage suitable for refreshing. Also included is a P-well region where N-channel MOSFETs of a peripheral circuit are formed. This P-well region is applied with a back bias voltage of an absolute value smaller than that applied to the P-type well of the memory array section. A P-type well section, where there are formed N-channel MOSFETs of an input circuit or an output circuit connected with external terminals, is applied with a back bias voltage of an absolute value large enough to provide a measure of protection against undershoot, while the refresh characteristics are improved by reducing the leakage current between the source/drain region connected with a capacitor and the P-type well, to thereby raise the operation speed of the peripheral circuit.

Abstract: In a semiconductor memory device which is intended to have a smaller sense amplifier forming area to match with small-sized bit lines, first bit lines BL (e.g., BL2a) are formed on a first layer, and lines M2 (e.g., M2a) are formed on a second layer and connected to the first bit lines in a first connecting area located between a first memory cell area and a sense amplifier area. Second bit lines BL (e.g., BL1c) are formed on the first layer, and lines M2 (e.g., M2c) are formed on the second layer and connected to the second bit lines in a second connecting area located between a second memory cell area and the sense amplifier area. As a result, the lines M2 on the second layer can have a smaller line interval.

Abstract: When a DRAM enters an operation mode in which only a data storing operation is performed, a check bit for error detection and correction for plural data is generated and stored. Refresh operation is performed in a refresh cycle which is made long within an allowable range of an error occurrence by an error correcting operation using the check bit. Before the DRAM returns to the normal operation mode from the data holding operation mode, an error bit is corrected by using the data and the check bit.

Abstract: When a DRAM enters an operation mode in which only a data storing operation is performed, a check bit for error detection and correction for plural data is generated and stored. Refresh operation is performed in a refresh cycle which is made long within an allowable range of an error occurrence by an error correcting operation using the check bit. Before the DRAM returns to the normal operation mode from the data holding operation mode, an error bit is corrected by using the data and the check bit.

Abstract: A memory cells are arranged at all intersections of a first word line and one line of a bit-line pair and all intersections of a second word line and the other line of the bit-line pair by arranging in parallel the first word line and the second word line consisting of different layers in the row direction with an identical pitch, and, also, alternately arranging the first word line and the second word line at an interval equal to a half of the pitch in the horizontal direction. Moreover, the selection MISFET of the memory cell is formed to have the vertical construction and the bit line located at the upper side of the substrate, where a channel region is formed, is shielded with a conductive film, a part of which forms the gate electrode.

Abstract: The memory cells are arranged to all intersections of the first word line and one line of the bit-line pair and all intersections of the second word line and the other line of the bit-line pair by arranging in parallel the first word line and the second word line consisting of different layers in the row direction with the identical pitch and also alternately arranging the first word line and the second word line at an interval equal to a half of the pitch in the horizontal direction. Moreover, the selection MISFET of the memory cell is formed in the vertical construction and the bit line located at the upper side of the substrate where a channel region is formed is shielded with a conductive film, a part of which forms the gate electrode.

Abstract: In a semiconductor memory device which is intended to have a smaller sense amplifier forming area to match with small-sized bit lines, first bit lines BL (e.g., BL2a) are formed on a first layer, and lines M2 (e.g., M2a) are formed on a second layer and connected to the first bit lines in a first connecting area located between a first memory cell area and a sense amplifier area. Second bit lines BL (e.g., BL1c) are formed on the first layer, and lines M2 (e.g., M2c) are formed on the second layer and connected to the second bit lines in a second connecting area located between a second memory cell area and the sense amplifier area. As a result, the lines M2 on the second layer can have a smaller line interval.

Abstract: A semiconductor IC device includes, in a substrate, a P-type well region having a dynamic memory array section and applied with a reduced back bias voltage suitable for refreshing. Also included is a P-well region where N-channel MOSFETs of a peripheral circuit are formed. This P-well region is applied with a back bias voltage of an absolute value smaller than that applied to the P-type well of the memory array section. A P-type well section, where there are formed N-channel MOSFETs of an input circuit or an output circuit connected with external terminals, is applied with a back bias voltage of an absolute value large enough to provide a measure of protection against undershoot, while the refresh characteristics are improved by reducing the leakage current between the source/drain region connected with a capacitor and the P-type well, to thereby raise the operation speed of the peripheral circuit.

Abstract: When a DRAM enters an operation mode in which only a data storing operation is performed, a check bit for error detection and correction for plural data is generated and stored. Refresh operation is performed in a refresh cycle which is made long within an allowable range of an error occurrence by an error correcting operation using the check bit. Before the DRAM returns to the normal operation mode from the data holding operation mode, an error bit is corrected by using the data and the check bit.

Abstract: A semiconductor integrated circuit device includes in a P-type well region containing a memory substrate a array section in which dynamic memory cells are arranged in a matrix. The P-type well region is fed with a back bias voltage whose absolute value is reduced so as to be the most suitable for the refresh characteristics. Also included is a P-well region wherein there are formed N-channel MOSFETs of a peripheral circuit this P-well region is fed with a back bias voltage whose absolute value is smaller than that of the potential fed to the P-type well of the memory array section, considering the high-speed operation. A P-type well section, wherein there is formed are N-channel MOSFETs of an input circuit or an output circuit connected with external terminals, is fed with a back bias voltage whose absolute value is made large considering an undershoot voltage. The P-type well region provided with the memory array section is fed with a requisite minimum back bias voltage.

Abstract: A method of manufacturing a semiconductor integrated circuit device includes the steps of constructing a plurality of lead frames having leads which each include an inner portion and an outer portion and electrically connecting a semiconductor chip to the inner portions of the leads of each frame. The lead frames are then stacked one above each other to form a vertical stack and plates are then inserted between each of the lead frames with each plate having an opening in the center whereby a central cavity is formed in the stack. The stack is then placed between a top mold member and a bottom mold member and a resin is injected into the central cavity whereupon the resin is cured to form a single resin package encapsulating the semiconductor chips. The resin package is then released from the mold members.

Abstract: A semiconductor memory device is provided which includes a substrate arrangement which is suitable for forming a large number of types of DRAMs having different package specifications, different bit structure and different operating modes. In conjunction with this, the bonding pads are arranged at optimum locations for accommodating the different package types. Various layout arrangements are also provided to minimize space and to improve access time. Additional features are provided, including improved output buffer circuitry, protection circuitry and testing methods to facilitate operation of the semiconductor memory device.