Patents by Inventor Hidetoshi Iwai
Hidetoshi Iwai has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 5736277Abstract: Pattern data of a phase shift mask can be inspected: (101) by separating and laying out pattern data of a phase shift mask in an actual pattern data layer, an auxiliary pattern data layer and a phase shift pattern data layer; (102) by inspecting and correcting only the data of the actual pattern of the actual pattern data layer; (103) by making data of an estimated pattern estimated to be transferred to a semiconductor wafer from the data of the synthetic data of the correct actual pattern data, the auxiliary pattern data and the phase shift pattern data, which are inspected and corrected; and (104) by comparing the estimated pattern data and the actual pattern data to inspect the data of the auxiliary pattern and the phase shift pattern.Type: GrantFiled: July 11, 1996Date of Patent: April 7, 1998Assignee: Hitachi, Ltd.Inventors: Toshitsugu Takekuma, Toshio Suzuki, Hidetoshi Iwai, Masamichi Ishihara
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Patent number: 5689465Abstract: To provide a semiconductor memory device characterized by the fact that it can prevent errors in the redundant memory address coincidence signal generating circuit caused by the intrinsic resistance of the fuse in the fuse decoder, and it has a redundant mechanism for generating the high-speed address coincidence signal.It has multiple logic gate means and fuses programmable by the gate output. The output signal of each fuse is wired to generate address coincidence signal.Type: GrantFiled: August 26, 1996Date of Patent: November 18, 1997Assignee: Texas Instruments IncorporatedInventors: Shunichi Sukegawa, Takumi Nasu, Hidetoshi Iwai
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Patent number: 5654577Abstract: A semiconductor integrated circuit device includes in a substrate a P-type well region containing a memory array section in which dynamic memory cells are arranged in a matrix. The P-type well region is fed with a back bias voltage whose absolute value is reduced so as to be the most suitable for the refresh characteristics. Also included is a P-well region wherein there are formed N-channel MOSFETs of a peripheral circuit this P-well region is fed with a back bias voltage whose absolute value is smaller than that of the potential fed to the P-type well of the memory array section, considering the high-speed operation. A P-type well section, wherein there is formed are N-channel MOSFETs of an input circuit or an output circuit connected with external terminals, is fed with a back bias voltage whose absolute value is made large considering an undershoot voltage. The P-type well region provided with the memory array section is fed with a requisite minimum back bias voltage.Type: GrantFiled: June 7, 1995Date of Patent: August 5, 1997Assignee: Hitachi, Ltd.Inventors: Masayuki Nakamura, Kazuyuki Miyazawa, Hidetoshi Iwai
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Patent number: 5629898Abstract: A period pulse corresponding to the shortest information retention time of those of dynamic memory cells is counted to form a refresh address to be assigned to a plurality of word lines. A carry signal outputted from the refresh address counter is divided by a divider. For each of said plurality of word lines assigned with the refresh address, one of a short period corresponding to an output pulse of a timer or a long period corresponding to the divided pulse from the divider is stored in a storage circuit as refresh time setting information. A memory cell refresh operation to be performed by the refresh address is made valid or invalid for each word line according to the refresh time setting information stored in the storage circuit and the refresh time setting information itself is made invalid by the output pulse of the divider.Type: GrantFiled: February 29, 1996Date of Patent: May 13, 1997Assignee: Hitachi, Ltd.Inventors: Youji Idei, Katsuhiro Shimohigashi, Masakazu Aoki, Hiromasa Noda, Katsuyuki Sato, Hidetoshi Iwai, Makoto Saeki, Jun Murata, Yoshitaka Tadaki, Toshihiro Sekiguchi, Osamu Tsuchiya
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Patent number: 5610089Abstract: Disclosed is a semiconductor device having an internal circuit protected by an electrostatic protective circuit, the internal circuit and electrostatic protective circuit being formed on the same semiconductor substrate. The internal circuit includes MIS elements and has a double-diffused drain structure, while the protective circuit has a single-diffused drain structure. The internal circuit can be, e.g., a DRAM, and the protective circuit can have diffused resistors and clamping MIS elements. The single-diffused drain structure can be formed in the protective circuit on the semiconductor substrate, while providing double-diffused drain structure in the internal circuit on the same substrate, by: (1) scanning the ion implanting apparatus to avoid ion implantation of the first ions into the region of the protective circuit, and/or (2) forming a photoresist film over the region of the protective circuit to prevent ion implanation of the first ions into the protective circuit region.Type: GrantFiled: April 27, 1995Date of Patent: March 11, 1997Assignee: Hitachi, Ltd.Inventors: Hidetoshi Iwai, Kazumichi Mitsusada, Masamichi Ishihara, Tetsuro Matsumoto, Kazuyuki Miyazawa, Hisao Katto, Kousuke Okuyama
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Patent number: 5594279Abstract: A semiconductor device in which shield wiring is arranged between the semiconductor substrate and the power source wiring for supplying the power source potential or ground potential. Noise, as represented by variations in the potential of the semiconductor substrate, is substantially prevented from transferring to the aforementioned power source wiring by the shield wiring. In one aspect, shield wiring 1 is arranged between Vss wiring for supplying potential to the various circuits on the semiconductor substrate and substrate 7. This shield wiring 1 is connected to grounding lead frame 18 via M1 intra-chip wiring 4, M2 intra-chip wiring 5, connecting part 40, bonding pad 3 and bonding wire 8.Type: GrantFiled: November 10, 1993Date of Patent: January 14, 1997Assignees: Texas Instruments Incorporated, Hitachi Ltd.Inventors: Yutaka Itou, Hidetoshi Iwai, Toshiyuki Sakuta, Takumi Nasu, Tomohiro Suzuki
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Patent number: 5565285Abstract: Pattern data of a phase shift mask can be inspected: (101) by separating and laying out pattern data of a phase shift mask in an actual pattern data layer, an auxiliary pattern data layer and a phase shift pattern data layer; (102) by inspecting and correcting only the data of the actual pattern of the actual pattern data layer; (103) by making data of an estimated pattern estimated to be transferred to a semiconductor wafer from the data of the synthetic data of the correct actual pattern data, the auxiliary pattern data and the phase shift pattern data, which are inspected and corrected; and (104) by comparing the estimated pattern data and the actual pattern data to inspect the data of the auxiliary pattern and the phase shift pattern.Type: GrantFiled: September 27, 1995Date of Patent: October 15, 1996Assignee: Hitachi, Ltd.Inventors: Toshitsugu Takekuma, Toshio Suzuki, Hidetoshi Iwai, Masamichi Ishihara
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Patent number: 5550394Abstract: To provide a semiconductor memory device characterized by the fact that it can prevent errors in the redundant memory address coincidence signal generating circuit caused by the intrinsic resistance of the fuse in the fuse decoder, and it has a redundant mechanism for generating the high-speed address coincidence signal. It has multiple logic gate means and fuses programmable by the gate output. The output signal of each fuse is wired to generate address coincidence signal.Type: GrantFiled: June 18, 1993Date of Patent: August 27, 1996Assignees: Texas Instruments Incorporated, Hitachi, Ltd.Inventors: Shunichi Sukegawa, Takumi Nasu, Hidetoshi Iwai
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Patent number: 5534723Abstract: Disclosed is a semiconductor device having an internal circuit protected by an electrostatic protective circuit, the internal circuit and electrostatic protective circuit being formed on the same semiconductor substrate. The internal circuit includes MIS elements and has a double-diffused drain structure, while the protective circuit has a single-diffused drain structure. The internal circuit can be, e.g., a DRAM, and the protective circuit can have diffused resistors and clamping MIS elements. The single-diffused drain structure can be formed in the protective circuit on the semiconductor substrate, while providing double-diffused drain structure in the internal circuit on the same substrate, by: (1) scanning the ion implanting apparatus to avoid ion implantation of the first ions into the region of the protective circuit, and/or (2) forming a photoresist film over the region of the protective circuit to prevent ion implantation of the first ions into the protective circuit region.Type: GrantFiled: April 27, 1995Date of Patent: July 9, 1996Assignee: Hitachi, Ltd.Inventors: Hidetoshi Iwai, Kazumichi Mitsusada, Masamichi Ishihara, Tetsuro Matsumoto, Kazuyuki Miyazawa, Hisao Katto, Kousuke Okuyama
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Patent number: 5498897Abstract: A semiconductor integrated circuit comprising a MOSFET having a metal wiring layer formed via an insulating film above and along the gate electrode of the MOSFET. The MOSFET is structured such that its channel length is small or channel width is large, and an input signal is applied from at least both end sides of the gate electrode thereof. Since the metal wiring layer for the input signal is formed on the gate electrode of the MOSFET, high-speed operation is possible without increasing the layout area. FIG. 1.Type: GrantFiled: July 1, 1994Date of Patent: March 12, 1996Assignees: Texas Instruments Incorporated, Hitachi Ltd.Inventors: Katsuo Komatsuzaki, Masayasu Kawamura, Hidetoshi Iwai
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Patent number: 5485425Abstract: There is provided a semiconductor memory device having a redundant column. This memory device has a redundant column disposed in the direction of the Y-system address, a ROM accessed by using an X-system address, a Y-system address signal having a defective cell included in the cells therein being electrically written into the ROM, a comparator circuit for comparing a signal read out from this ROM with a Y-system address signal and outputting a coincidence signal upon coincidence, and a defect relieving circuit responsive to output of the coincidence signal from this comparator circuit to cause selection of the redundant column of Y system instead of the Y-system address selection device.Type: GrantFiled: January 20, 1995Date of Patent: January 16, 1996Assignees: Hitachi, Ltd., Texas Instruments IncorporatedInventors: Hidetoshi Iwai, Masaya Muranaka, Takumi Nasu, Shunichi Sukegawa
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Patent number: 5483490Abstract: An arrangement is provided for preventing DC defects in a memory or logic device after switching to a redundant circuit, improving the product yield of the device by cutting a leakage current path through a defective element or circuit. The cutting points formed by the predetermined wirings as a whole or a part thereof are provided to the device. A probe test of the formed chip is executed under the wafer condition by predetermined test equipment, and wiring correction data regarding the cutting of the cutting points is generated based on the result of test. Moreover, this wiring correction data is transmitted in an on-line fashion to the wiring correction equipment so that the corresponding cutting points can be cut. The wiring correction equipment can be formed by an EB direct writing apparatus, an FIB apparatus or a laser repair apparatus.Type: GrantFiled: December 1, 1993Date of Patent: January 9, 1996Assignee: Hitachi, Ltd.Inventors: Hidetoshi Iwai, Masamichi Ishihara, Kazuya Ito, Wataru Arakawa, Yoshinobu Nakagome
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Patent number: 5458998Abstract: Pattern data of a phase shift mask can be inspected: (101) by separating and laying out pattern data of a phase shift mask in an actual pattern data layer, an auxiliary pattern data layer and a phase shift pattern data layer; (102) by inspecting and correcting only the data of the actual pattern of the actual pattern data layer; (108) by making data of an estimated pattern estimated to be transferred to a semiconductor wafer from the data of the synthetic data of the correct actual pattern data, the auxiliary pattern data and the phase shift pattern data, which are inspected and corrected; and (104) by comparing the estimated pattern data and the actual pattern data to inspect the data of the auxiliary pattern and the phase shift pattern.Type: GrantFiled: May 21, 1992Date of Patent: October 17, 1995Assignee: Hitachi, Ltd.Inventors: Toshitsugu Takekuma, Toshio Suzuki, Hidetoshi Iwai, Masamichi Ishihara
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Patent number: 5436484Abstract: Disclosed is a semiconductor device having an internal circuit protected by an electrostatic protective circuit, the internal circuit and electrostatic protective circuit being formed on the same semiconductor substrate. The internal circuit includes MIS elements and has a double-diffused drain structure, while the protective circuit has a single-diffused drain structure. The internal circuit can be, e.g., a DRAM, and the protective circuit can have diffused resistors and clamping MIS elements. The single-diffused drain structure can be formed in the protective circuit on the semiconductor substrate, while providing double-diffused drain structure in the internal circuit on the same substrate, by: (1) scanning the ion implanting apparatus to avoid ion implantation of the first ions into the region of the protective circuit, and/or (2) forming a photoresist film over the region of the protective circuit to prevent ion implanation of the first ions into the protective circuit region.Type: GrantFiled: October 29, 1993Date of Patent: July 25, 1995Assignee: Hitachi, Ltd.Inventors: Hidetoshi Iwai, Kazumichi Mitsusada, Masamichi Ishihara, Tetsuro Matsumoto, Kazuyuki Miyazawa, Hisao Katto, Kousuke Okuyama
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Patent number: 5436483Abstract: Disclosed is a semiconductor device having an internal circuit protected by an electrostatic protective circuit, the internal circuit and electrostatic protective circuit being formed on the same semiconductor substrate. The internal circuit includes MIS elements and has a double-diffused drain structure, while the protective circuit has a single-diffused drain structure. The internal circuit can be, e.g., a DRAM, and the protective circuit can have diffused resistors and clamping MIS elements. The single-diffused drain structure can be formed in the protective circuit on the semiconductor substrate, while providing double-diffused drain structure in the internal circuit on the same substrate, by: (1) scanning the ion implanting apparatus to avoid ion implantation of the first ions into the region of the protective circuit, and/or (2) forming a photoresist film over the region of the protective circuit to prevent ion implanation of the first ions into the protective circuit region.Type: GrantFiled: October 29, 1993Date of Patent: July 25, 1995Assignee: Hitachi, Ltd.Inventors: Hidetoshi Iwai, Kazumichi Mitsusada, Masamichi Ishihara, Tetsuro Matsumoto, Kazuyuki Miyazawa, Hisao Katto, Kousuke Okuyama
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Patent number: 5426613Abstract: A semiconductor memory device is provided which includes a substrate arrangement which is suitable for forming a large number of types of DRAMs having different package specifications, different bit structure and different operating modes. In conjunction with this, the bonding pads are arranged at optimum locations for accommodating the different package types. Various layout arrangements are also provided to minimize space and to improve access time. Additional features are provided, including improved output buffer circuitry, protection circuitry and testing methods to facilitate operation of the semiconductor memory device.Type: GrantFiled: November 6, 1992Date of Patent: June 20, 1995Assignees: Hitachi, Ltd., Hitachi VLSI Engineering Corp.Inventors: Yasushi Takahashi, Hidetoshi Iwai, Satoshi Oguchi, Hisashi Nakamura, Hiroyuki Uchiyama, Toshitugu Takekuma, Shigetoshi Sakomura, Kazuyuki Miyazawa, Masamichi Ishihara, Ryoichi Hori, Takeshi Kizaki, Yoshihisa Koyama, Haruo Ii, Masaya Muranaka, Hidetomo Aoyagi, Hiromi Matsuura
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Patent number: 5410507Abstract: A dynamic RAM provided with a data retention mode intended for low power consumption is provided. In the data retention mode, the current supply capabilities of voltage generation circuits which generate decreased voltage, increased voltage, reference voltage, etc., are limited in the range in which information retention operation in memory cells can be maintained, and the number of selected memory mats in the data retention mode is increased with respect to that of memory mats selected in the normal read/write mode and refresh mode. Special modes such as the data retention mode are set by combining an address strobe signal and other control signals and dummy CBR refresh is executed to release the special mode.Type: GrantFiled: November 16, 1992Date of Patent: April 25, 1995Assignee: Hitachi, Ltd.Inventors: Masanori Tazunoki, Shigetoshi Sakomura, Toshitsugu Takekuma, Yutaka Ito, Kazuya Ito, Wataru Arakawa, Hidetoshi Iwai, Toshiyuki Sakuta, Masamichi Ishihara
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Patent number: 5359561Abstract: A semiconductor memory device is provided which includes a plurality of data lines, at least one redundant data line, one common data line, a plurality of column switches installed between the plurality of data lines and the redundant data line and one common data line, and a column decoder for controlling the plurality of column switches. The column decoder operates to turn the column switch on. The column switch is connected to a plurality of data lines, excluding any defective data and redundant data lines during the test mode state.Type: GrantFiled: April 23, 1992Date of Patent: October 25, 1994Assignee: Hitachi, Ltd.Inventors: Shigetoshi Sakomura, Kazuya Ito, Hidetoshi Iwai, Toshiyuki Sakuta, Masamichi Ishihara, Tomoshi Matsumoto, deceased
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Patent number: 5289416Abstract: An arrangement is provided for preventing DC defects in a memory or logic device after switching to a redundant circuit, improving the product yield of the device by cutting a leakage current path through a defective element or circuit. The cutting points formed by the predetermined wirings as a whole or a part thereof are provided to the device. A probe test of the formed chip is executed under the wafer condition by predetermined test equipment, and wiring correction data regarding the cutting of the cutting points is generated based on the result of test. Moreover, this wiring correction data is transmitted in an on-line fashion to the wiring correction equipment so that the corresponding cutting points can be cut. The wiring correction equipment can be formed by an EB direct writing apparatus, an FIB apparatus or a laser repair apparatus.Type: GrantFiled: January 14, 1992Date of Patent: February 22, 1994Assignee: Hitachi, Ltd.Inventors: Hidetoshi Iwai, Masamichi Ishihara, Kazuya Ito, Wataru Arakawa, Yoshinobu Nakagome
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Patent number: 5287000Abstract: According to one aspect of the present invention, a semiconductor chip, which can be mounted in a zigzag in-line type package (ZIP) partially using a tabless lead frame, includes bonding pads arranged on the chip so that the chip can be applied also to other different types of packages. These different types of packages include a small out-line J-bent type package (SOJ) which uses a lead frame with tab, and a dual in-line type package (DIP) which uses a tabless lead frame. Further, a plurality of bonding pad pairs are provided amongst the bonding pads on the chip, each pad of such bonding pad pairs having the same function as the other pad associated therewith thereby duplicating a common function in different bonding pads on the semiconductor chip so as to make the semiconductor chip compatible with a variety of or different types of packages.Type: GrantFiled: March 26, 1991Date of Patent: February 15, 1994Assignees: Hitachi, Ltd., Hitachi VLSI Engineering Corp.Inventors: Yasushi Takahashi, Kazuyuki Miyazawa, Hidetoshi Iwai, Masaya Muranaka, Yoshitaka Kinoshita, Satoru Koshiba