Patents by Inventor Hidetoshi Masuda

Hidetoshi Masuda has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 12100551
    Abstract: A ceramic electronic device includes a multilayer body in which each of a plurality of dielectric layers and each of a plurality of internal electrode layers are alternately stacked. In at least a part of a cover layer and side margins, a concentration of a specific metal of at least one of Ag, As, Au, Bi, Co, Cr, Cu, Fe, Ge, In, Ir, Mo, Os, Pd, Pt, Re, Rh, Ru, Se, Sn, Te, W or Zn is lower on an outer side than on a side of the multilayer body.
    Type: Grant
    Filed: September 14, 2022
    Date of Patent: September 24, 2024
    Assignee: TAIYO YUDEN CO., LTD
    Inventor: Hidetoshi Masuda
  • Publication number: 20240280550
    Abstract: A method for analyzing a sample containing a carboxylic acid anhydride includes, in a stated order, a first step of causing the sample to pass through a column together with a first mobile phase to detect a carboxylic acid anhydride eluted from the column in supercritical fluid chromatography, and a second step of causing a second mobile phase to pass through the column by switching the mobile phase from the first mobile phase to the second mobile phase after a lapse of a retention time of the carboxylic acid anhydride to detect at least one of a carboxylic acid ester and a carboxylic acid eluted from the column. The first mobile phase is a mixture of carbon dioxide and an organic solvent having no hydroxyl group, and the second mobile phase is a mixture of carbon dioxide, an acid, and an organic solvent having a hydroxyl group.
    Type: Application
    Filed: February 9, 2024
    Publication date: August 22, 2024
    Applicant: SHIMADZU CORPORATION
    Inventors: Yusuke Masuda, Hidetoshi Terada
  • Publication number: 20240249888
    Abstract: A ceramic electronic device includes a multilayer structure in which each of a plurality of dielectric layers of which a main component is ceramic and each of a plurality of internal electrode layers are alternately stacked. The plurality of internal electrode layers include Ni and Sn. Each of an upper section and a lower section of the plurality of internal electrode layers includes multiple internal electrode layers each having a Sn concentration higher than that of each internal electrode layer of a center section interposed between the upper and lower sections in a stacking direction, which are constituted by top 5% or more and bottom 5% or more of the plurality of internal electrode layers, respectively.
    Type: Application
    Filed: March 1, 2024
    Publication date: July 25, 2024
    Inventor: Hidetoshi MASUDA
  • Patent number: 11948751
    Abstract: A ceramic electronic device includes a multilayer structure in which each of a plurality of dielectric layers of which a main component is ceramic and each of three or more of internal electrode layers are alternately stacked. The three or more of internal electrode layers include Ni and Sn. An internal electrode layer having a larger Sn concentration is closer to an outermost edge in a stacking direction than an internal electrode layer having a smaller Sn concentration and being located on a center side of the stacking direction, in a relationship of at least two of the three or more of internal electrode layers.
    Type: Grant
    Filed: January 7, 2022
    Date of Patent: April 2, 2024
    Assignee: TAIYO YUDEN CO., LTD.
    Inventor: Hidetoshi Masuda
  • Patent number: 11948753
    Abstract: A manufacturing method of a multilayer ceramic electronic device includes: forming each of stack units by forming each of internal electrode patterns on each of dielectric green sheets, the each of internal electrode patterns including Ni, Sn and Au; forming a multilayer structure by stacking the each of stack units; and firing the multilayer structure, whereby each internal electrode layer is formed from the each of internal electrode patterns and each dielectric layer is formed from the each of the dielectric green sheets wherein, in the each internal electrode layer, an Au concentration near each interface between the each internal electrode layer and the each dielectric layer is larger than an Au concentration in each center portion in a thickness direction.
    Type: Grant
    Filed: June 1, 2023
    Date of Patent: April 2, 2024
    Assignee: TAIYO YUDEN CO., LTD.
    Inventors: Kazuki Yamada, Kotaro Mizuno, Yoichi Kato, Hidetoshi Masuda
  • Patent number: 11915882
    Abstract: A ceramic electronic device includes a multilayer chip in which a dielectric layer and an internal electrode layer are alternately stacked. Concentration peaks of two or more types of metals different from a main component metal of the internal electrode layer exist at different positions in a stacking direction of the dielectric layer and the internal electrode layer, between the dielectric layer and the internal electrode layer.
    Type: Grant
    Filed: August 30, 2022
    Date of Patent: February 27, 2024
    Assignee: TAIYO YUDEN CO., LTD.
    Inventors: Hidetoshi Masuda, Kotaro Mizuno, Koichi Tsukagoshi
  • Patent number: 11830674
    Abstract: A ceramic electronic device includes a multilayer chip in which a plurality of dielectric layers and a plurality of internal electrode layers are stacked. The plurality of internal electrode layers include Au. Each of the plurality of internal electrode layers includes an Au-containing layer of which an Au concentration with respect to all detected elements is 5 at % or more, on an interface between the each of the plurality of internal electrode layers and a dielectric layer next to the each of the plurality of internal electrode layers. A relationship of C?500×t/T is satisfied when a thickness of the each of the plurality of internal electrode layers is T nm, a thickness of the Au-containing layer is t nm, and an Au concentration with respect to a total of Ni and Au in a whole of the each of the plurality of internal electrode layers is C at %.
    Type: Grant
    Filed: April 25, 2022
    Date of Patent: November 28, 2023
    Assignee: TAIYO YUDEN CO., LTD.
    Inventors: Hidetoshi Masuda, Minoru Ryu, Teruo Atsumi
  • Patent number: 11787652
    Abstract: The medium transporting device is arranged so as to face the feeder for feeding the medium in the transporting direction and the surface of the medium transported in the transporting direction, and detects the motion of the medium in the two-dimensional coordinate system including the first axis and the second axis. The two-dimensional sensor is provided in a state in which the first axis and the second axis are inclined with respect to the transporting direction.
    Type: Grant
    Filed: September 9, 2019
    Date of Patent: October 17, 2023
    Assignee: Seiko Epson Corporation
    Inventor: Hidetoshi Masuda
  • Publication number: 20230326680
    Abstract: A manufacturing method of a multilayer ceramic electronic device includes: forming each of stack units by forming each of internal electrode patterns on each of dielectric green sheets, the each of internal electrode patterns including Ni, Sn and Au; forming a multilayer structure by stacking the each of stack units; and firing the multilayer structure, whereby each internal electrode layer is formed from the each of internal electrode patterns and each dielectric layer is formed from the each of the dielectric green sheets wherein, in the each internal electrode layer, an Au concentration near each interface between the each internal electrode layer and the each dielectric layer is larger than an Au concentration in each center portion in a thickness direction.
    Type: Application
    Filed: June 1, 2023
    Publication date: October 12, 2023
    Inventors: Kazuki YAMADA, Kotaro MIZUNO, Yoichi KATO, Hidetoshi MASUDA
  • Publication number: 20230317373
    Abstract: A ceramic electronic device includes a multilayer chip in which each of a plurality of dielectric layers and each of a plurality of internal electrode layers are alternately stacked. There are a concentration peak of a first metal and a concentration peak of a second metal at different positions in a stacking direction of the plurality of internal electrode layers and the plurality of dielectric layers between a dielectric layer and an internal electrode layer next to the dielectric layer, the first metal and the second metal being different from a main component metal of the plurality of internal electrode layers. The second metal is easier to ionize than the first metal. The concentration peak of the second metal is closer to the dielectric layer than the concentration peak of the first metal.
    Type: Application
    Filed: March 23, 2023
    Publication date: October 5, 2023
    Inventors: Riki SUEMASA, Hidetoshi MASUDA
  • Publication number: 20230298820
    Abstract: A ceramic electronic device includes a multilayer chip in which dielectric layers and internal electrode layers are alternately stacked. The internal electrode layers include a main component element and a sub-element. The dielectric layers include a plurality of crystal grains. A segregation portion, in which the sub-element is segregated in shell portions and a grain boundary of the plurality of crystal grains and a sub-element concentration is 1.5 times or more as that in an entire of each of the dielectric layers, is formed. near an interface between each of the internal electrode layers and each of the dielectric layers, each of the internal electrode layers has a high concentration layer, in which the sub-element concentration is 1.5 times or more as that in an entire of each of the internal electrode layers.
    Type: Application
    Filed: March 7, 2023
    Publication date: September 21, 2023
    Inventor: Hidetoshi MASUDA
  • Patent number: 11710601
    Abstract: A ceramic electronic device includes a multilayer chip in which a plurality of dielectric layers of which a main component is ceramic and a plurality of internal electrode layers are stacked. The plurality of internal electrode layers include Ni, Sn and Au.
    Type: Grant
    Filed: July 9, 2021
    Date of Patent: July 25, 2023
    Assignee: TAIYO YUDEN CO., LTD.
    Inventors: Kazuki Yamada, Kotaro Mizuno, Yoichi Kato, Hidetoshi Masuda
  • Publication number: 20230128407
    Abstract: A ceramic electronic device includes a multilayer body in which each of a plurality of dielectric layers and each of a plurality of internal electrode layers are alternately stacked. In at least a part of a cover layer and side margins, a concentration of a specific metal of at least one of Ag, As, Au, Bi, Co, Cr, Cu, Fe, Ge, In, Ir, Mo, Os, Pd, Pt, Re, Rh, Ru, Se, Sn, Te, W or Zn is lower on an outer side than on a side of the multilayer body.
    Type: Application
    Filed: September 14, 2022
    Publication date: April 27, 2023
    Inventor: Hidetoshi MASUDA
  • Publication number: 20230084921
    Abstract: A ceramic electronic device includes a multilayer chip in which a dielectric layer and an internal electrode layer are alternately stacked. Concentration peaks of two or more types of metals different from a main component metal of the internal electrode layer exist at different positions in a stacking direction of the dielectric layer and the internal electrode layer, between the dielectric layer and the internal electrode layer.
    Type: Application
    Filed: August 30, 2022
    Publication date: March 16, 2023
    Inventors: Hidetoshi MASUDA, Kotaro MIZUNO, Koichi TSUKAGOSHI
  • Publication number: 20220384113
    Abstract: A capacitor that can make a failure mode into an open mode even when a short circuit caused by insulation breakdown occurs in a dielectric layer is provided. The capacitor includes: a substrate; an MIM structure disposed on the Substrate, the MIM structure including a dielectric layer, a bottom electrode layer disposed on one side of the dielectric layer and composed of a first conductive material, and a top electrode layer disposed on the other side of the dielectric layer; a first external electrode disposed on the substrate; a second external electrode disposed on the substrate; and a connection conductor connecting between the bottom electrode layer and the first external electrode, the connection conductor including a first contact portion contacting the substrate.
    Type: Application
    Filed: September 28, 2020
    Publication date: December 1, 2022
    Inventors: Yoshinari TAKE, Yoshio AOYAGI, Hidetoshi MASUDA
  • Publication number: 20220384109
    Abstract: A ceramic electronic device includes a multilayer chip in which a plurality of dielectric layers and a plurality of internal electrode layers are stacked. The plurality of internal electrode layers include Au. Each of the plurality of internal electrode layers includes an Au-containing layer of which an Au concentration with respect to all detected elements is 5 at % or more, on an interface between the each of the plurality of internal electrode layers and a dielectric layer next to the each of the plurality of internal electrode layers. A relationship of C?500×t/T is satisfied when a thickness of the each of the plurality of internal electrode layers is T nm, a thickness of the Au-containing layer is t nm, and an Au concentration with respect to a total of Ni and Au in a whole of the each of the plurality of internal electrode layers is C at %.
    Type: Application
    Filed: April 25, 2022
    Publication date: December 1, 2022
    Inventors: Hidetoshi MASUDA, Minoru RYU, Teruo ATSUMI
  • Publication number: 20220238280
    Abstract: A ceramic electronic device includes a multilayer structure in which each of a plurality of dielectric layers of which a main component is ceramic and each of three or more of internal electrode layers are alternately stacked. The three or more of internal electrode layers include Ni and Sn. An internal electrode layer having a larger Sn concentration is closer to an outermost edge in a stacking direction than an internal electrode layer having a smaller Sn concentration and being located on a center side of the stacking direction, in a relationship of at least two of the three or more of internal electrode layers.
    Type: Application
    Filed: January 7, 2022
    Publication date: July 28, 2022
    Inventor: Hidetoshi MASUDA
  • Patent number: 11343406
    Abstract: A control portion performs a predetermined detection process on a first image from a first reading portion and a second image from a second reading portion. When the detection process on the each image is successful, the control portion performs, based on a value of an image processing variable specified from a detection result, predetermined image processing on the each image, When the detection process on the image of one side fails, a value of an image processing variable for the image of one side is specified based on a value of an image processing variable specified from the detection result for the image of the other side for which detection is successful. Based on the specified value of the image processing variable, image processing is performed on the image of one side.
    Type: Grant
    Filed: March 29, 2021
    Date of Patent: May 24, 2022
    Assignee: Seiko Epson Corporation
    Inventor: Hidetoshi Masuda
  • Publication number: 20220139630
    Abstract: A ceramic electronic device includes a multilayer chip in which a plurality of dielectric layers of which a main component is ceramic and a plurality of internal electrode layers are stacked. The plurality of internal electrode layers include Ni, Sn and Au.
    Type: Application
    Filed: July 9, 2021
    Publication date: May 5, 2022
    Inventors: Kazuki YAMADA, Kotaro MIZUNO, Yoichi KATO, Hidetoshi MASUDA
  • Publication number: 20220030129
    Abstract: The medium transporting device is arranged so as to face the feeder for feeding the medium in the transporting direction and the surface of the medium transported in the transporting direction, and detects the motion of the medium in the two-dimensional coordinate system including the first axis and the second axis. The two-dimensional sensor is provided in a state in which the first axis and the second axis are inclined with respect to the transporting direction.
    Type: Application
    Filed: September 9, 2019
    Publication date: January 27, 2022
    Inventor: Hidetoshi MASUDA