Patents by Inventor Hidetoshi Masuda

Hidetoshi Masuda has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9076595
    Abstract: A capacitor includes a dielectric layer having a first plane, a second plane opposite to the first plane, and first and second through-holes communicated with the first plane and the second plane; a first external conductor layer disposed on the first plane; a second external conductor layer disposed on the second plane; a first internal electrode formed in the first through-hole, connected to the first external electrode layer, disposed in the second hole diameter part at a tip and separated from the second external electrode layer; and a second internal electrode formed in the second through-hole, connected to the second external electrode layer, and separated from the first external electrode layer.
    Type: Grant
    Filed: August 29, 2013
    Date of Patent: July 7, 2015
    Assignee: Taiyo Yuden Co., Ltd.
    Inventor: Hidetoshi Masuda
  • Patent number: 9007741
    Abstract: A capacitor includes a dielectric layer, a first external electrode layer, a second external electrode layer, a first internal electrode portion, a second internal electrode portion, and an adsorbing portion. The first internal electrode portion is provided on a first through-hole portion, one end of the first internal electrode portion being connected to the first external electrode layer. The second internal electrode portion is provided on a second through-hole portion, one end of the second internal electrode portion being connected to the second external electrode layer. The adsorbing portion adsorbs the first external electrode layer and the second external electrode layer, the adsorbing portion being provided on a third through-hole portion.
    Type: Grant
    Filed: June 5, 2013
    Date of Patent: April 14, 2015
    Assignee: Taiyo Yuden Co., ltd.
    Inventors: Hidetoshi Masuda, Yoshinari Take
  • Patent number: 8964090
    Abstract: A control apparatus for controlling an image capture apparatus includes a communication unit and a control unit. The communication unit transmits a first command to the image capture apparatus if a predetermined area in a captured image received from the image capture apparatus and a pointer operated by an operation unit are overlapped. The communication unit transmits a second command to the image capture apparatus if a button of the operation unit is clicked in a state that the predetermined area and the pointer are overlapped.
    Type: Grant
    Filed: March 1, 2013
    Date of Patent: February 24, 2015
    Assignee: Canon Kabushiki Kaisha
    Inventors: Hidetoshi Masuda, Toshiaki Ueguri
  • Patent number: 8917491
    Abstract: One object is to provide a porous capacitor having increased insulation reliability. In accordance with one aspect, the porous capacitor includes: a first conductor layer and a second conductor layer opposed to each other at a predetermined distance; a dielectric layer made of an oxidized valve metal and disposed between the first conductor layer and the second conductor layer; a large number of holes formed through the dielectric layer and oriented substantially orthogonal to the first conductor layer and the second conductor layer; and first electrodes and second electrodes formed of a conductive material filled in the holes; and insulation parts insulating the first electrodes from the second conductor layer and insulating the second electrodes from the first conductor layer. The thicknesses of the first conductor layer and the second conductor layer are equal to or greater than half of the inner diameter of the holes.
    Type: Grant
    Filed: March 22, 2013
    Date of Patent: December 23, 2014
    Assignee: Taiyo Yuden Co., Ltd
    Inventors: Hidetoshi Masuda, Kenichi Ota
  • Patent number: 8837111
    Abstract: A capacitor forming unit according to one embodiment includes a dielectric plate with a plurality of through holes; a first conductor film formed on an upper surface of the dielectric plate; a first insulator film formed on the front end portion of the upper surface of the dielectric plate; a second conductor film formed on a lower surface of the dielectric plate; a second insulator film formed on the rear end portion of the lower surface of the dielectric plate; first electrode rods disposed in some of the through holes; and second electrode rods disposed in the remaining through holes where the first electrode rods are not disposed. The first electrodes are electrically connected to the first conductor film and electrically insulated from the second conductor film. The second electrode rods are electrically connected to the second conductor film and are electrically insulated from the first conductor film.
    Type: Grant
    Filed: March 16, 2012
    Date of Patent: September 16, 2014
    Assignee: Taiyo Yuden Co., Ltd.
    Inventors: Yoshinari Take, Hidetoshi Masuda, Kenichi Ota
  • Publication number: 20140226257
    Abstract: A capacitor according to the present invention includes a dielectric layer, a first external electrode layer, a second external electrode layer, a first internal electrode, and a second internal electrode. The dielectric layer is formed of a metal oxide having a crystalline structure and includes a first surface, a second surface on the opposite side to the first surface, and a plurality of through holes communicating with the first surface and the second surface. The first external electrode layer is disposed on the first surface. The second external electrode layer is disposed on the second surface. The first internal electrode is formed in through holes, and is connected to the first external electrode layer. The second internal electrode is formed in the through holes, and is connected to the second external electrode layer.
    Type: Application
    Filed: January 27, 2014
    Publication date: August 14, 2014
    Applicant: TAIYO YUDEN CO., LTD.
    Inventors: Yoshinari TAKE, Hidetoshi MASUDA
  • Patent number: 8767374
    Abstract: A capacitor and a manufacturing method thereof with improved capacitance density, simplified production process, and/or improved high frequency characteristic without having to form a nano-scale pattern are provided. A capacitor element 12 includes a dielectric layer made of porous oxide substrate, first and second internal electrodes formed within holes of the porous oxide substrate, a first external electrode electrically connected to the first internal electrode, a second external electrode electrically connected to the second internal electrodes.
    Type: Grant
    Filed: August 24, 2012
    Date of Patent: July 1, 2014
    Assignee: Taiyo Yuden Co., Ltd.
    Inventor: Hidetoshi Masuda
  • Patent number: 8769170
    Abstract: Managing commands that have not been executed is simplified while maintaining a state in which real-time commands can be executed. A printer 2 has a write control unit 21A that writes received commands to a receive buffer 31, a command execution unit 21B that executes the written commands, and a real-time command execution unit 21C that executes written commands that are real-time commands. The printer 2 enters a full-buffer mode as needed by the capacity of available storage space in the receive buffer 31, and when in the full-buffer mode the write control unit 21A cyclically writes commands to an auxiliary space created in the receive buffer, and the real-time command execution unit 21C reads and executes real-time commands from the auxiliary space.
    Type: Grant
    Filed: September 16, 2011
    Date of Patent: July 1, 2014
    Assignee: Seiko Epson Corporation
    Inventors: Masayo Miyasaka, Hidetoshi Masuda
  • Publication number: 20140153157
    Abstract: A capacitor includes a dielectric layer having a first plane, a second plane opposite to the first plane, and a plurality of through-holes communicated with the first and second planes; a first external electrode layer disposed on the first plane; a second external electrode layer disposed on the second plane; a first internal electrode having first and second electrode portions, the first and second electrode portions being formed of a first conductive material, and a second conductive material, respectively, the second electrode material connecting the first electrode portion with the first external electrode layer, the second conductive material having a smaller Young's modulus than the first conductive material, the first internal electrode being formed in a part of the plurality of through-holes; and a second internal electrode formed in another part of the plurality of through-holes, the second internal electrode being connected to the second external electrode layer.
    Type: Application
    Filed: December 4, 2013
    Publication date: June 5, 2014
    Applicant: Taiyo Yuden Co., Ltd.
    Inventor: Hidetoshi MASUDA
  • Publication number: 20140063690
    Abstract: A capacitor includes a dielectric layer having a first plane, a second plane opposite to the first plane, and first and second through-holes communicated with the first plane and the second plane; a first external conductor layer disposed on the first plane; a second external conductor layer disposed on the second plane; a first internal electrode formed in the first through-hole, connected to the first external electrode layer, disposed in the second hole diameter part at a tip and separated from the second external electrode layer; and a second internal electrode formed in the second through-hole, connected to the second external electrode layer, and separated from the first external electrode layer.
    Type: Application
    Filed: August 29, 2013
    Publication date: March 6, 2014
    Applicant: Taiyo Yuden Co., Ltd.
    Inventor: Hidetoshi MASUDA
  • Publication number: 20140009866
    Abstract: There is provided a capacitor including a dielectric layer having a first plane, a second plane opposite to the first plane, and a plurality of through-holes communicated with the first plane and the second plane; a first external conductor layer disposed on a part of the first plane; a second external conductor layer disposed on the second plane; a third external conductor layer disposed on another part of the first plane; a first internal conductor housed in a part of a plurality of the through-holes and connected to the first external conductor layer; a second internal conductor housed in another part of a plurality of the through-holes and connected to the second external conductor layer; and a third internal conductor housed in the other part of a plurality of the through-holes and connected to the second external conductor layer and the third external conductor layer.
    Type: Application
    Filed: July 2, 2013
    Publication date: January 9, 2014
    Inventors: Hidetoshi MASUDA, Shinya MASUNO, Yoshinari TAKE
  • Publication number: 20130335880
    Abstract: There is provided a capacitor including a dielectric layer having a first plane, a second plane opposite to the first plane, and a plurality of through-holes communicated with the first plane and the second plane, including a plurality of arrangement regions where arrangement directions of the plurality of through-holes are same; a first external electrode layer disposed on the first plane; a second external electrode layer disposed on the second plane; a first internal electrode housed in a part of the plurality of through-holes and connected to the first external electrode layer; and a second internal electrode housed in a part of the plurality of through-holes and connected to the second external electrode layer.
    Type: Application
    Filed: June 11, 2013
    Publication date: December 19, 2013
    Inventor: Hidetoshi MASUDA
  • Publication number: 20130329339
    Abstract: A capacitor includes a dielectric layer, a first external electrode layer, a second external electrode layer, a first internal electrode portion, a second internal electrode portion, and an adsorbing portion. The first internal electrode portion is provided on a first through-hole portion, one end of the first internal electrode portion being connected to the first external electrode layer. The second internal electrode portion is provided on a second through-hole portion, one end of the second internal electrode portion being connected to the second external electrode layer. The adsorbing portion adsorbs the first external electrode layer and the second external electrode layer, the adsorbing portion being provided on a third through-hole portion.
    Type: Application
    Filed: June 5, 2013
    Publication date: December 12, 2013
    Inventors: Hidetoshi MASUDA, Yoshinari TAKE
  • Publication number: 20130329337
    Abstract: A capacitor includes a dielectric layer, a first external electrode layer, a second external electrode layer, a first internal electrode portion, a second internal electrode portion, and a close contact portion. The first internal electrode portion is provided on a first through-hole portion, one end of the first internal electrode portion being connected to the first external electrode layer. The second internal electrode portion is provided on a second through-hole portion, one end of the second internal electrode portion being connected to the second external electrode layer. The close contact portion brings at least any one of the first external electrode layer and the second external electrode layer into close contact with the dielectric layer, the close contact portion being provided on a third through-hole portion.
    Type: Application
    Filed: June 5, 2013
    Publication date: December 12, 2013
    Inventors: Hidetoshi MASUDA, Yoshinari TAKE
  • Publication number: 20130321984
    Abstract: One object is to provide a porous capacitor having increased insulation reliability. In accordance with one aspect, the porous capacitor includes: a first conductor layer and a second conductor layer opposed to each other at a predetermined distance; a dielectric layer made of an oxidized valve metal and disposed between the first conductor layer and the second conductor layer; a large number of holes formed through the dielectric layer and oriented substantially orthogonal to the first conductor layer and the second conductor layer; and first electrodes and second electrodes formed of a conductive material filled in the holes; and insulation parts insulating the first electrodes from the second conductor layer and insulating the second electrodes from the first conductor layer. The thicknesses of the first conductor layer and the second conductor layer are equal to or greater than half of the inner diameter of the holes.
    Type: Application
    Filed: March 22, 2013
    Publication date: December 5, 2013
    Applicant: TAIYO YUDEN CO., LTD.
    Inventors: Hidetoshi MASUDA, Kenichi Ota
  • Patent number: 8555474
    Abstract: A method of manufacturing a capacitor includes: anodizing a metal substrate in two stages by applying two different voltage so as to make first and second holes having different pitches, distributed randomly in an oxide substance; filling the first and second holes with an electrode material, respectively, to form first and second electrodes; connecting the first electrodes to a conductive layer formed on one surface of the oxide substance; and connecting the second electrodes to another conductive layer formed on another surface of the oxide substance.
    Type: Grant
    Filed: July 22, 2011
    Date of Patent: October 15, 2013
    Assignee: Taiyo Yuden Co., Ltd.
    Inventors: Hidetoshi Masuda, Taisei Irieda, Masaru Kurosawa, Kotaro Mizuno
  • Patent number: 8531816
    Abstract: A capacitor forming unit includes a dielectric plate, a first conductor film formed on a plate upper surface region other than front and rear end portions, a first insulator film formed on the upper surface front end portion, a second insulator film formed on the upper surface rear end portion, a second conductor film formed on a plate lower surface region other than front and rear end portion, a third insulator film formed on the front end portion lower surface, and a fourth insulator film formed on the lower surface rear end portion. One or more first electrode rods are disposed in through holes, and electrically connected to the first conductor film and electrically insulated from the second conductor film. One or more second electrode rods are disposed in other through holes, and electrically connected to the second conductor film and electrically insulated from the first conductor film.
    Type: Grant
    Filed: March 16, 2012
    Date of Patent: September 10, 2013
    Assignee: Taiyo Yuden Co., Ltd
    Inventors: Yoshinari Take, Hidetoshi Masuda, Kenichi Ota
  • Publication number: 20130148259
    Abstract: One object is to provide a capacitor that can have an improved capacitance value without sacrificing a dielectric breakdown voltage and a method for manufacturing the capacitor, or a capacitor that can have an improved dielectric breakdown voltage without sacrificing the capacitance value and a method for manufacturing the capacitor. In accordance with one aspect, a capacitor includes a porous dielectric layer obtained by metal anodization; columnar electrodes filled into the holes of the dielectric layer; a first external electrode formed on one principal surface of the dielectric layer and electrically conductive to some of the columnar electrodes; and second external electrodes formed on the other principal surface of the dielectric layer and electrically conductive to columnar electrodes not electrically conductive to the first external electrode. The second external electrodes are disposed so as to be electrically isolated from each other.
    Type: Application
    Filed: May 26, 2011
    Publication date: June 13, 2013
    Applicant: TAIYO YUDEN CO., LTD.
    Inventors: Hidetoshi Masuda, Kenichi Ota
  • Publication number: 20130092424
    Abstract: [Problem to be Solved] Provided are a stress buffer layer which satisfactorily releases stress acting on a joint portion, allowing an improvement in mounting reliability, and a method for producing the stress buffer layer. [Solution] A stress buffer sheet 10 is constituted by arranging external conductive layers 16A and 16B on the front and rear main surfaces of a through electrode layer 13 in which a resin 12 is filled between many columnar internal electrodes (metal pillars) 14. The columnar internal electrodes 14 are formed using a porous oxide base material 30 formed by anodic oxidation of valve metal; the oxide base material 30 is selectively removed after the internal electrodes 14 have been formed, and the resin 12 having a Young's modulus smaller than the oxide base material 30 is filled in a resultant void space. The internal electrode 14 has a high aspect ratio and a remarkable flexibility. The resin 12 has a small Young's modulus and can be deformed together with the internal electrode 14.
    Type: Application
    Filed: March 24, 2011
    Publication date: April 18, 2013
    Applicant: TAIYO YUDEN CO., LTD.
    Inventor: Hidetoshi Masuda
  • Publication number: 20130083454
    Abstract: A capacitor and a manufacturing method thereof with improved capacitance density, simplified production process, and/or improved high frequency characteristic without having to form a nano-scale pattern are provided. A capacitor element 12 includes a dielectric layer made of porous oxide substrate, first and second internal electrodes formed within holes of the porous oxide substrate, a first external electrode electrically connected to the first internal electrode, a second external electrode electrically connected to the second internal electrodes.
    Type: Application
    Filed: August 24, 2012
    Publication date: April 4, 2013
    Applicant: TAIYO YUDEN CO., LTD.
    Inventor: Hidetoshi MASUDA